2022 Program Grid

Registration Opens Daily at 7:30 AM.

DVCon Europe 2022 will follow all local guidelines related to COVID. Click here to learn more about the restriction in Munich.

 Forum 4Forum 5Forum 6Forum 7Großer Saal
8:00 - 8:15 AMOpening Session
(Ballsaal) 
8:15 - 9:15 AMKeynote: Developing the Chip-to-Cloud Architecture for the Most Desirable Cars
(Ballsaal) 
9:15 - 10:30 AMPanel: 5G Chip Design Challenges and their Impact on Verification
(Ballsaal) 
10:30 - 10:45 AMAttendee Break
(Großer Saal)

Exhibit Floor Open

10:45 - 12:15 PM

P1.1 
Programmable Analysis of RISC-V Processor Simulations using WAL

Automated Creation of Reusable Generators for Analog IC Design with the Intelligent IP Method

A Reconfigurable Interface Architecture to Protect System IP

P2.1
A novel and efficient methodology to expedite complex SoC DV closure by leveraging modularly architectured scalable environment

Using Open-Source EDA in an Industrial Design Flow

Soumak: How rich descriptions enable early detection of hookup issues

P3.1
Building Confidence in System level CPU Cache Coherency Verification for Complex SoC's through a Configurable, Flexible and Portable Test-Bench

Unified firmware debug throughout SoC development lifecycle”

An Accelerated System Level CPU Verification through Simulation-Emulation Co-Existence

P4.1
SAWD: Systemverilog Assertions Waveform-Based Development Tool

Register Testing – Exploring Tests, Register  Model Libraries, Sequences and Backdoor Access

uvm_mem – challenges of using UVM infrastructure in a hierachical verification

12:15 - 1:15 PMLunch 
(Großer Saal)
1:15 - 2:45 PM

P1.2
A UVM SystemVerilog Testbench for 5G/LTE Multi-Standard RF Transceiver

A novel approach to hardware controlled power aware verification with optimised power consumption techniques at SoC

Modelling of UVC Monitor Class as a Finite State Machine for a Packet-Based Interface

P2.2
Automate Interrupt Checking with UVM Macros and Python

Poster Presentations
Reset Your Reset Domain Crossing (RDC) Verification with Machine Learning

A novel approach to expedite MCU verification and enabling efficacious inter-processor communication in a multiprocessor SoC

A Novel Approach to Expedite Verification Cycle using an Adaptive and Performance Optimized Simulator Independent Verification Platform Development

A novel approach to standardize reusable Modular Plug and Play Skeleton Structure (MPPSS) to expedite verification closure

Types of Robustness Test According to DO-254 Guideline for Avionic Systems

P3.2
Development and Verification of RISC-V Based DSP Subsystem IP:   Case Study

A Cross-domain Heterogeneous ABV-Library for Mixed-signal Virtual Prototypes in SystemC/AMS

A Framework for the Execution of Python Tests in SystemC and Specman Testbenches

P4.2
How creativity kills reuse - A modern take on UVM/SV TB architectures

Reusable Verification Environment for a RISC-V Vector Accelerator

The cost of standard verification methodology implementations

2:45 - 3:15 PMAttendee Break / Poster Session 
(Großer Saal)
3:15 - 4:45 PM

P1.3
How to achieve verification closure on configurable code by combining static analysis and dynamic testing

Challenges and Solutions for Creating Virtual Platforms of FPGA and SASIC Designs

SIM-V - Fast, Parallel RISC-V Simulation for Rapid Software Verification

P2.3
Efficient Methodology for Mutation-Coverage-Collection of Formal-Property-Checking

How the Right Mindset Increases Quality in RISC-V Verification

Overcoming SystemVerilog Assertions limitations through temporal decoupling and automation

P3.3
Closing the gap between requirement management and circuit design by requirement tracing

A Generic Configurable Error Injection Agent for On-Chip Memories

Agile Approaches to ASIC Verification (A3V) – A Novel Agile Flow in Functional Verification

P4.3
Automated Configuration of System Level C-Based CPU Test-Bench in Modern SoCs: A Novel  Framework

Generic Core-Monitor for Hardware/Software Co-Debugging targeting Emulation Platform

Improving Simulation Regression Efficiency  using a Machine Learning-based Method  in Design Verification

4:45 - 5:45 PM Panel: Are processor/SoC discontinuities turning verification on its head?
(Ballsaal) 
5:45 - 6:30 PMClosing Session & Best Paper Award
(Ballsaal) 

SCED-2022-Logo-500px

SystemC Evolution Day 2022

Workshop on the Evolution of SystemC Standards, held on 8 December 2022

The seventh SystemC Evolution Day is a full-day, technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. In several in-depth sessions, selected current and future standardization topics around SystemC will be discussed in order to accelerate their progress for inclusion in Accellera/IEEE standards.

SystemC Evolution Day is intended as a lean, user-centric, hands-on forum bringing together experts from the SystemC user community and the Accellera Working Groups to advance SystemC standards.

Event information

Date: 8 December 2022 (day after DVCon Europe 2022)
Time: 09:30 - 17:30 CET
Location: Holiday Inn Munich City Centre, Hochstrasse 3, 81669 Munich, Germany

Registration

Registration fee is €50. Register here.

Organization Team:

  • Ola Dahl, Ericsson (Chair)
  • Martin Barnasconi, NXP
  • Jerome Cornet, STMicroelectronics
  • Christian Sauer, Cadence
  • Mark Burton, Qualcomm
  • Peter de Jager, Intel

Program

The main theme this year is Evolution and Ecosystem: Besides the developments of the SystemC standard and its implementations, we like to broaden our view to see and learn how SystemC is used, or could be used, in other system modeling and simulation environments around us.

Exploring this bigger ecosystem, and understanding the role of SystemC in such ecosystem, is vital to identify new requirements and features to be developed as part of the SystemC ecosystem or beyond, by means of adapters, interfaces or other intercommunication concepts.

Agenda

Tentative schedule - subject to change

Time (CEST)  TitlePresenter(s), Organization
09:30 - 10:15Welcome & Introduction – Theme: Evolution and EcosystemMartin Barnasconi, Accellera Technical Committee Chair
10:15 - 10:30Coffee break 
10:30 - 11:30IEEE 1666-202x SystemC Sneak PeekJerome Cornet, IEEE P1666 Working Group Chair
11:30 - 12:00Q&A 
12:00 - 13:30Lunch 
13:30 – 14:00Accellera + SystemC Working Group updateMartin Barnasconi, Accellera Technical Committee Chair
14:00 - 14:30Virtualization and Emulation with QEMU and SystemCFrançois-Frédéric Ozog, Shokubai
14:30 - 15:00Q&A 
15:00 - 15:15Coffee break 
15:15 - 15:45Distributed simulation and SystemCMark Burton, Qualcomm Inc.
15:45 - 16:45Panel & Discussion:
System modeling and simulation – now and in the future
Panelists:
  Mark Burton, Qualcomm Inc.
  François-Frédéric Ozog, Shokubai
  Manfred Thanner, NXP
  Bart Vanthournout, Synopsys
Moderator:
  Jakob Engblom, Intel
16:45 - 17:15SystemC Evolution OutlookMartin Barnasconi, Accellera Technical Committee Chair
17:15 - 17:30Wrap-up & closureAll