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2023 Program Grid

Registration will open daily 30 minutes before the 1st session.

 Forum 4Forum 5Forum 6Forum 7Großer Saal
8:30 - 8:45 AMOpening Session
(Ballsaal) 
8:45 - 9:45 AMKeynote Speaker: Philippe Notton
Energy-efficient High Performance Compute, at the heart of Europe
(Ballsaal)
9:45 - 10:00 AMAttendee Break
(Großer Saal)

Exhibit Floor Open

10:00 - 11:30 AM

T1.1

IP-XACT Tutorial

T2.1

Accellera Functional Safety Working Group Update and Next Steps

T3.1

Scalable agile processor verification using SystemC UVM friends

T4.1

SysML v2: An overview with demonstration

11:30 - 11:45 AMAttendee Break
(Großer Saal)
11:45 - 1:15 PM

T1.2

AI-Driven Debug and Verification Management
logo_synopsys

T2.2

Shift your HDL design left and keep your eyes on team code metrics in FPGA & ASIC design and verification
Sigasi

T3.2

Model-Based Approach for Developing Optimal HW/SW Architectures for AI systems
Siemens-Logo

T4.2

New Methods in Core and SoC Verification based on RISC-V
breker-logo4-300x138

1:15 - 2:15 PMLunch
(Großer Saal)
2:15 - 3:45 PM

T1.3

IP-XACT Industrial Practices

T2.3

Migrating from UVM to UVM-MS

T3.3

Making the impossible possible: CDC and RDC closure with abstracts from different tools

T4.3

Open-Source Virtual Platforms for Industry and Research 

3:45 - 4:00 PMAttendee Break
(Großer Saal)
4:00 - 5:30 PM

T1.4

How to leverage the power of MATLAB from Functional Verification Test Benches
mathworks

T2.4

The Expanding role of Static Signoff in Verification Coverage
real intent logo

T3.4

Exploring New Frontiers of High-Performance Verification with UVM-AMS
cadence

T4.4

Double Software Verification Shift-left by combining Model-Based Design and Virtual ECUs’
Infineon-Logo.svg
logo_synopsysmathworks

5:30 - 7:00 PMReception
(Großer Saal)
7:30 - 10:30 PMAnniversary Dinner
sponsored by 
AMIQ_EDA_logo
 Forum 4Forum 5Forum 6Forum 7Forum 8 Großer Saal
8:00 - 8:15 AMOpening Session
(Ballsaal)
8:15 - 9:15 AMKeynote Speaker: Michaela Blott
Pervasive and Sustainable AI with Adaptive Computing
(Ballsaal)
9:15 - 10:15 AMPanel: "All AI All the Time” Poses New Challenges for Traditional Verification
(Ballsaal)
10:15 - 10:30 AMAttendee Break
(Großer Saal)

Exhibit Floor Open

10:30 - 12:00 PM

P1.1 

A Hybrid Approach For Interrupts Verification

Verification of an AXI cache controller using multi-thread approach based on OOP design patterns

[Short] Hybrid Emulation for faster Android Home screen bring up and Software Development

[Short] A perfect blend of verification techniques, platforms, and AI-empowered debugging in Ethernet Subsystem Verification

P2.1

SV VQC UDN for Modeling Switch-Capacitor-based Circuits

Self-Triggering Mechanism for Modeling a Low-Dropout Regulator with Load Capacitor

**[Short] On the Performance Differences of SystemC and SystemC AMS: A Guideline for Real Number Modeling and Beyond

**[Short] A tool for Investigating Cyber-Physical Systems via SystemC AMS Virtual Prototypes Derived from SysML Models

P3.1

[Short] A Model-Based Reusable Framework to Parallelize Hardware and Software Development

Fuzzing Firmware running on Intel® Simics® Virtual Platforms

[Short] 400G IPU Case Study: Demonstrating Shift-left of Soft Logic RTL Development on Real World Design using Intel Agilex FPGA SystemC Model

**Co-Design of Automotive Boardnet Topology and Architecture

P4.1

Verilator + UVM-SystemC: a match made in heaven

Closed-Loop Model-First SoC Development With the Intel Simics Simulator

** [Short] A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural Networks

** [Short] Large-scale Gatelevel Optimization Leveraging Property Checking

P5.1

[Short] An Improved Methodology for Debugging UPF Issues at SoC level Power Aware Simulations

Unified Architecture of L1 and L2 Cache with Low Power Extensions for Multi-Core UVM-based Library Package

Virtual testing of overtemperature protection algorithms in automotive smart fuses

[Short] Efficient Verification of a RADAR SoC Using Formal and Simulation-Based Methods

12:00 - 1:00 PMLunch 
(Großer Saal)
1:00 - 2:30 PM

P1.2

A scalable VIP component to increase robstuness of co-verification within an ASIC

A Novel Framework to Accelerate System Validation on Emulation

[Short] Low-Power Validation Framework for Standard Cell Library including Front-End and Back-End implementation

[Short] Initialization Techniques for D-Flip-Flop Based Scan Chain with Scan Flush Architecture in Gate-Level Simulation

P2.2

System-Level Simulation of a SPAD-Based Time-of-Flight Sensor in SystemVerilog

**Clock Tree Design Considerations in The Presence of Asymmetric Transistor Aging

**Variation-Aware Performance Verification of Analog Mixed-Signal Systems

P3.2

[Short] Fault-injection-Enhanced Virtual Prototypes Enable Early SW Development for Automotive Applications

HW-SW-Coverification as part of CI/CD

Integration Verification of Safety Components in Automotive Chip Modules

[Short] Virtual ECUs with QEMU and SystemC TLM-2.0

P4.2

Accelerating Complex System Simulation using Parallel SystemC and FPGAs

** [Short] 
Design Verification of the Quantum Control Stack

Control Flow Analysis for Bottom-up Portable Models Creation

** [Short] MetaPSS: An Automation Framework for Generation of Portable Stimulus Model

P5.2

Accelerate Functional Coverage Closure Using Machine-Learning-Based Test Selection

A UVM Test-bench Skeleton Leveraging the Event Pool and Sequence Layering

Towards a Hybrid Verification Environment for Signal Processing SoCs

2:30 - 2:45 PMAttendee Break
(Großer Saal)
2:45 - 3:45 PM

P1.3

The Three Body Problem

Break the SoC with UVM Dynamically Generated Program Code

P2.3

Bridging the gap between system-level and chip-level performance optimization

**MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells

P3.3

Reverse Hypervisor - Faster SoC Simulation, an approach to Arm on Arm on Arm

Efficient Debugging on Virtual Prototype using Reverse Engineering Method

P4.3

Verification Methodology for Efficient PVT(Process, Voltage and Temperature)Variation Analysis & Characterisation for Thermal and Power Aggressor IPs in a 3D SOC.

Smart TSV (Thru Silicon Via) Repair Automation in 3DIC designs

P5.3

Plug and Play Verification: Leveraging Block-Level Components for Seamless Top-Level Integration

The Road to Robustness: Addressing LPDDR5X PHY Verification Challenges with DFE

3:45 - 4:00 PMAttendee Break
(Großer Saal)
4:00 - 5:00 PM

P1.4

Planning for RISC-V Success: Verification Planning and Functional Coverage lead to quality RISC-V processor IP

A Novel Approach to Standardise Verification Configurations using YAML

P2.4

**Evaluation of the RISC-V Floating Point Extensions

**DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VPs

P3.4

Grid-based Mapping and Analysis of a GoogLeNet CNN using MapGL Editor

VPSim : Virtual Prototyping Simulator with best accuracy & execution time trade-off for High Performance Computing systems evaluation and benchmarking

P4.4

Testbench Linting – open-source way

Effective Design Verification – Constrained Random with Python and Cocotb

P5.4

An Elegant scoreboard eco-system deploying UVM Callbacks, Parameterization for Multimedia designs from Imaging perspective

Pragmatic Formal Verification Methodology for Clock Domain Crossing (CDC)

5:00 - 6:00 PMPanel: The Great Verification Chiplet Challenge
(Ballsaal) 
6:00 - 6:30 PMClosing Session & Best Paper Award (Ballsaal) 

** These are papers from the research track
Author presentations are 30 minutes in length unless listed as "[Short]" which will be a 15 minute presentation.

SystemC Evolution Day 2023

Workshop on the Evolution of SystemC Standards: 16 November 2023

The eight SystemC Evolution Day is a full-day, technical workshop on the evolution of SystemC standards to advance the SystemC ecosystem. In several in-depth sessions, selected current and future standardization topics around SystemC will be discussed in order to accelerate their progress for inclusion in Accellera/IEEE standards.

SystemC Evolution Day is intended as a lean, user-centric, hands-on forum bringing together experts from the SystemC user community and the Accellera Working Groups to advance SystemC standards.

Event information

Date: 16 November 2023 (day after DVCon Europe 2023)
Time: 09:30 - 17:15 CET
Location: Holiday Inn Munich City Centre, Hochstrasse 3, 81669 Munich, Germany

Registration

  • Early bird registration fee (till 1 October): €35.
  • Registration fee after 1 October: €50.

Register here.

Organization Team:

  • Martin Barnasconi, NXP
  • Jerome Cornet, STMicroelectronics
  • Mark Burton, Qualcomm
  • Peter de Jager, Intel

Theme this year

The main theme this year is The future of SystemC: With the release of the updated SystemC standard IEEE 1666-2023 in September, the community will reflect on the future of SystemC and discuss the possible and essential steps in the SystemC standardization journey.

Agenda

Note: This is a face-to-face event, so no online presentations / participation possible

Time (CET)  TitlePresenter(s), Organization
09:30 - 10:00Welcome & Introduction – Theme: Evolution and EcosystemMark Burton, SystemC Evolution Day Chair
10:00 - 11:00SystemC Language Working Group and IEEE 1666-2023 UpdateLaurent Maillet-Contoz, SystemC LWG Chair
11:00 – 11:30Accellera SystemC Working Groups updateMartin Barnasconi, Accellera Technical Committee Chair
11:30 – 12:00New Federated Simulation Standard Proposed Working GroupMark Burton, FSS PWG Vice-chair
12:00 - 12:30Trace features in SystemCLukas Jünger, MachineWare GmbH
Eyck Jentzsch, MINRES Technologies
12:30 - 14:00Lunch 
14:00 - 14:30RISC-V VP++: Unlocking the vast Linux ecosystem for Open
Source RISC-V Virtual Prototypes:
From Fast Bootup, VNC, Vector Extension to 3D-Games
Daniel Große, JKU Linz, Austria
14:30 - 15:30The Future of SystemCDiscussion - All
15:30 - 17:00SystemC Configuration Control Inspection : Where do we go from here !Lukas Jünger, CCI WG Chair
17:00 - 17:15Wrap-up & closure 

Contact us

systemc-evolution-day@lists.accellera.org