Author Presentations

A comparison of methodologies to simulate mixed-signal IC

A Methodology for Evaluating SI Artefacts in DDR4-3DS PHY using Channel Modelling

A Novel Approach to Functional Test Development and Execution using High-Speed IO

A Novel Approach To In-System SRAM Repair Verification in Embedded SoC to Bridge Gap between Test and Functional Mode

A Novel Approach to Reuse Firmware for Verification of Controller based Sub-Systems using PSS

Accelerated Coverage Closure by Utilizing Local Structure in the RTL Code

Achieving Faster Code Coverage Closure using High-Level Synthesis

Advance Approach for Formal Verification of Configurable Pulse Width Modulation Controller

An Analysis of Stimulus Techniques for Efficient Functional Coverage Closure

Bringing Reset Domains and Power Domains together – Set/Reset Flops Augmenting Complexities in Power-Aware RDC Verification

Centralized Regression Optimisation Toolkit (CROT) for expediting Regression Closure With Simulator Performance Optimisation

Chip-Level Analog Regression in Production

Democratizing Formal Verification

Detection of glitch-prone clock and reset propagation with automated formal analysis

Emulation based Power and Performance Workloads on ML NPUs

Five Ways to Make Your Specman Environment More Reusable and Configurable

Formal Property Verification of the Digital Section of an Ultra-Low Current Digitizer ASIC

Handling Asynchronous Reset(s) Testing by building reset-awareness into UVM testbench components

Language-Agnostic Communication for SystemC/TLM-2.0 Compliant Virtual Prototypes

Machine Learning based Structure Recognition in Analog Schematics for Constraints Generation

Machine Learning for Coverage Analysis in Design Verification

Maximize PSS Reuse with Unified Test Realization Layer Across Verification Environments

Method for early performance verification of hardware-accelerated embedded processor systems in RTL simulation

Netlist Paths: A tool for front-end netlist analysis

No Country For Old Men – A Modern Take on Metrics Driven Verification

One Testbench to Rule them all!

Optimizing Design Verification using Machine Learning: Doing better than Random

Resetting RDC Expectations – A Systematic Approach to Verifying Complex Configurable Designs

Reuse of System-Level Verification Components within Chip-Level UVM Environments

SimPy and Chips: A Discrete Event Simulation framework in python for large scale architectual modelling of machine intelligence accelerators

Successive Refinement – An approach to decouple Front-End and Back-end Power Intent

System-Level Register Verification and Debug

Testbench flexibility as a foundation for success

Unified Model/Hardware-in-the-Loop Methodology for Mixed-Signal System Design and Hardware Prototyping

Using Dependency Injection Design Pattern in Power Aware Tests

Using HLS to improve Design-for-Verification of multi-pipeline designs with resource sharing

Virtual Prototyping of Power Converter Systems based on AURIX™ using SystemC AMS

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