Also this year DVCon Europe covers a wide variety of technical tutorials at its first day. It offers an excellent opportunity for the engineering community to polish or expand their design and verification skills. I am very pleased to announce that the diversity of the tutorial program this year is more than ever: topics related formal verification, functional safety, virtual prototyping, debug, software-driven test, mixed-signal, and UVM; I expect most D&V engineers will have a true ‘luxury problem’ since there is too much to choose from.
Before sharing the overview of the tutorial program itself, let me first explain why DVCon Europe reserves a full day for its tutorial program. When we initiated DVCon Europe in 2014, one of our objectives was -and still is- to offer a stepping-stone for the semiconductor engineering community to enrich and grown their competences in design and verification. Many other European conferences did (and do) focus on academic and research topics, and we noticed that there were not many industry-centric conferences focusing on education and learning of practical design and verification methodologies and sharing ‘hands-on’ experiences. The DVCon Europe tutorial program is made such that engineers active in the field of design and verification can easily expand their skills in just one day!
Now the tutorial program itself. As always, many tutorials show practical experiences and give guidelines how to make optimal use of existing or emerging Accellera or IEEE standards. Examples of established EDA standards are SystemC, UVM, SystemVerilog, IP-XACT, etc. In addition, new and emerging standards are presented, such as UVM-SystemC and Portable Stimulus. Obviously, a nice standard and language is not enough; it needs to be supported by tools and a design flow. Therefore various EDA tool and IP providers will also present their products and solutions, focusing on the pure technical features and capabilities of their offering.
From DVCon Europe you can expect a strong contribution in electronic system-level design, virtual prototyping and the use of SystemC. The program covers different tutorials in this area: a SystemC standards update, the use of transaction level modelling (TLM), SystemC for High level synthesis (HLS) and tutorials on the benefits and use of virtual prototyping.
The application of the Universal Verification Methodology remains an attractive topic to talk about. A tutorial will explain the generation of a UVM register model using IP-XACT and techniques which are taken from the model-driven SW domain. Another tutorial will highlight how to automate the creation of testbenches and to save precious time by avoiding doing things manually. As testbenches and designs are getting more and more complex, one tutorial will present different debug capabilities and innovations which can be applied to the UVM world.
Two mixed-signal tutorials are included in the program. The application of the SystemC-AMS standard is explained for mixed-signal system level modelling for automotive applications. Obviously, the multidisciplinary nature of the mixed-signal domain requires that EDA tool providers will team-up to offer a solution for mixed-signal design and verification, which is presented in the another mixed-signal tutorial.
Design and verification for functional safety to comply to the ISO26262 standard is covered in two tutorials. EDA tool providers will present their technologies and design flow to improve design reliability by introducing techniques such as fault injection and analysis. Furthermore, the use formal verification is presented to improve the efficiency and effectiveness of verification.
A special invited tutorial has been added to the program, which highlights the challenges and solutions of having more firmware embedded in electronic systems. The tutorial shows the cooperation between universities with an industrial application focus on firmware design and automatic firmware generation.
To conclude, the 4th edition of DVCon Europe offers a rich and diverse tutorial program covering various design and verification standards, methodologies and tools for formal verification, functional safety, virtual prototyping, debug, software-driven test, mixed-signal, and UVM. So if you like to boost your skills in one or more of these areas, the DVCon Europe tutorial day is made for you!
We are looking forward to meet you at DVCon Europe in Munch!
DVCon Europe 2017 Tutorial Chair