DVCon Europe in its 4th year continues to provide high quality papers presented in technical sessions on day two of the conference. We really appreciate that the engineering community finds the time to submit industry focused technical papers, which forms the basis of the DVCon Europe technical program. A big thank you for submitting your paper to DVCon Europe!
We ensure the high quality of papers by a two phase review process. The Technical Program Committee (TPC) consists of three TPC Chairs and 32 reviewers from 18 different companies. DVCon Europe only accepts full (draft) papers in the first phase that present the main idea of the paper and show results. Real life examples are extremely desirable to highlight the nature of the conference - “from users, for users”. In the second phase of the review the TPC ensures that the authors deliver a high quality paper which follows the DVCon Europe standards and guidelines. To achieve this, TPC members act as shepherds to support the authors in the finalization of their paper. This year we are proud to present papers from 17 different companies, from three universities, from nine different countries, from Africa, Asia and Europe.
The program consists of verification sessions in the areas of software, firmware, formal verification, UVM, analog-mixed signal, low power, debugging, and functional coverage. Furthermore, design and system level topics will be presented in the areas of software design, architectural exploration, virtual prototyping, high-level synthesis, system-level design, and SystemC. The program is complemented with topics from the areas functional safety, specification automation, and IP-XACT.
In the verification area, for example, verification of resource-constrained firmware without the final hardware available and automatic firmware verification for automotive applications supporting functional safety are presented. One interesting topic will be the automatic generation of testbenches to reduce cycle time and foster reuse. Authors will talk on formal simulation techniques and verification IP for complex analog and mixed-signal behavior. Interesting topics on functional coverage as fast data manipulation and static checking of correctness of functional coverage models will be discussed. And finally, UVM is always a hot topic on RTL and on system level using SystemC
Safety verification is in everybody’s mind. We will see a paper on adaptation of UVM for safety verification requirements in the automotive and the IoT domain. Formal verification to complement simulation is a hot topic for functional safety to save engineering effort and speed up simulations for complex RTL and gate-level models. Another contribution will show a combination of metric-driven and constraint-random methods to make requirement-based verification more efficient.
The design area is at least as interesting as the verification area. Engineers deal with techniques for specifications to make software and hardware development more efficient from the very beginning and heterogeneous virtual prototyping for IoT applications. Also for the design area code generation is in the scope to foster reuse. An efficient hierarchical implementation approach for low-power designs will be presented. The topics even go beyond the electronical domain on SystemC simulations in combination with mechanical and magnetical effects.
You will enjoy the coffee breaks in the morning, afternoon, and between the sessions, to talk with the community on your hottest topics. Also this year many experts from a lot of different companies, universities, and research centers will attend the show. The exhibition gives you an excellent possibility to talk to EDA companies and address your problems.
We hope you participate at DVCon Europe in Munich on October 16th and 17th. The DVCon Europe Steering Team would be happy to see you at the event and is open for any discussions.
Dr. Matthias Bauer
DVCon Europe 2017 Technical Program Chair