DVCon Europe Blog

DVCon Europe: A Peak at the Future of SoC

Published on Tuesday, October 23rd, 2018
Dave Kelf Promotions Chair, DVCon Europe

From the range of EDA events, DVCon Europe stands out as one of the most forward-looking conferences. European engineering companies have a reputation for taking a long view when it comes to development methodology, which, in-turn, drives a strong interest in next-generation design and verification technology.

This year the program committee have excelled. In two short days attendees can hear about Artificial Intelligence and Machine Learning techniques, IoT architectural trends, and a staple of the conference, designing and verifying ISO 26262 Automotive devices. Where do a lot of these applications lead? The design and verification of next generation System-on-Chips (SoCs).

The 2018 DVCon Europe covers it all from the latest developments in the open instruction architecture RISC-V processor, system hardware and software verification, advanced UVM, AMS, next generation SystemC and so on. In two days, engineers will receive a crisp, clear preview of tomorrow’s SoCs.

This year’s two keynotes are particularly compelling, given the speaker’s experience in development methodologies. The well-known industry methodology driver Philippe Magarshack has moved from his long time role at ST looking after the company’s EDA solutions to special projects that include some of the most exciting work going on at the company. His keynote featuring IoT will no doubt draw on his experience to provide an entertaining and lively session.

Promising an equally fascinating discussion, Stefan Jockusch of Siemens PLM Software, will be covering the idea of the digital twin, a new concept in virtualization that shows great promise for modeling the most complex of electronic systems. As we exploit new algorithms and methodologies in applications such as automotive and AI, we enter uncharted waters and modeling offers the promise of greater predictability. An animated speaker, Stefan is sure to enlighten the audience on this intriguing topic.

New to the conference this year is a discussion on RISC-V. The unique, open instruction set architecture processor development has captured the attention of the industry at large, with a whole ecosystem of open source models and tools springing up around it. As the processor becomes attractive for hardcore commercial applications, with its ability to extend its base instruction set, an awareness of its potential adds a new string to the engineering bow, which could prove very useful. Three players in this space will be providing a fascinating tutorial on the use of RISC-V.

A discussion of RISC-V needs naturally to SoC design and verification methodologies in general. There is an apparent trend towards more functionality being designed and verified at the SoC level as complex IP, configurable processors, integrated firmware/software, and mixed signal components converge in these next generation platforms. On show this year are new techniques to realize these devices. Portable Stimulus, now an Accellera standard that holds much promise for SoC verification will be discussed. Several sessions looking at the verification of software tightly integrated to the hardware platform are also available. AMS solutions within the SoC are being taught with relevance for both analog and digital designers. Of course the conference is co-located with the SystemC Evolution Day, which will look at the latest techniques for architectural design and verification, and how these map to modern platforms.

Of course key SoC applications that require new techniques and design will be examined. Artificial Intelligence and Machine Learning has made a big entrance into the conference with an interesting looking tutorial from Intel providing instruction on ML applied to an LTE platform. Effective system modeling and virtual prototyping techniques for automotive components will be the subject of an expert panel. IoT will be coming up in several sessions. All of these applications drive advancements in SoC thinking from specialized processor instructions, enhanced system reliability or power control.

Matching advanced applications to evolutionary design techniques has become the hallmark of DVCon Europe, and attending the conference enables opportunities for every engineering specialization to improve their capabilities. This year’s show is brimming with topics for everyone. It’s not too late to sign up for this impressive event, register here!