Boosting Debug Productivity – Practical Applications of Debug Innovations in a UVM World

With the growing complexity of today’s SoCs, teams are facing intense time pressures for SoC verification closure, with engineers on the lookout for better verification and debug methodologies. As verification teams migrate to SystemVerilog and UVM class-based testbenches for higher efficiency and increased verification reuse across projects, debug methodology needs to scale accordingly to fully realize the benefits of this migration.
In this technical tutorial, we will focus on practical applications of Verdi debug innovations:

• Root causing a complex testbench bug with UVM-aware Reverse Debug natively integrated with simulation

• Techniques to quickly identify, isolate and debug failures using OneSearch, SmartLog and advanced SystemVerilog testbench debug capabilities

• Faster debug at higher levels of abstraction – from transaction debug for protocols to synchronized hardware software debug for earlier SW bring up
Attendees will take home an arsenal of techniques they can put to immediate use to significantly boost their debug productivity.

Event ID: 
e05bf12e-2f3b-4a49-ad72-b07a37e0887b
Event Type: 
Tutorial
Location: 
Forum 7
Event Time: 
Monday, October 16, 2017 -
16:00 to 17:30
Session Number: 
16
Session Number: 
16
Session Number Suffix: 
T
confID: 
234
Event Sponsor Image URL: 
https://dvcon-europe.org/sites/dvcon-europe.org/files/images/2016/SynopsysNoTag_WEB.png