27 - 28 October, 2020

Virtual Conference

DVCon Europe 2014 Proceedings

DVCon Europe 2014 Proceedings

Below are presentations, papers, and posters from DVCon Europe 2014. You may download individual items below or download all items at once.

Jump to: Keynote | Tutorials | Presentations & Papers | Poster & Papers


Tomorrow’s Smart Mobile Systems – by the Power of Ten Bernd Adler Slides


T1: European SystemC User Group Meeting

Part 1: SystemC Standards Update Trevor Wieman, Intel Corporation, United States Philipp Hartmann, OFFIS, Germany Tutorial
Part 2: UVM-SystemC Application in the Real World Stephan Schulz, Fraunhofer IIS/EAS, Germany Thilo Vörtler, Fraunhofer IIS/EAS, Germany Tutorial
Part 3: Virtual Platforms for Automotive: Use Cases, Benefits and Challenges Angela Kramer, Robert Bosch GmbH, Germany Tutorial

T2: Advanced UVM

Mark Litterick, Verilab Jason Sprott, Verilab Jonathan Bromley, Verilab Vanessa Cooper, Verilab Tutorial

T3: An Introduction to using Event-B for Cyber-Physical System Specification and Design

John Colley, University of Southampton, United Kingdom Michael Butler, University of Southampton, United Kingdom Tutorial

T4: Enabling Energy-Aware System Level Design with UPF-Based System Level Power Models

Tutorial not available for download. Ellie Burns, Mentor Graphics, United States Alan Gibbons, Synopsys, United Kingdom Josefina Hobbs, Synopsys, United States John Biggs, ARM, United Kingdom Richard Scales, Intel, France Erich Marschner, Mentor Graphics, United States

T5: Virtual Prototyping using SystemC TLM-2.0

John Aynsley, Doulos, United Kingdom Tutorial

T6: Requirements-driven Verification Methodology for Standards Compliance

Mike Bartley, Test and Verification Solutions Serrie Chapman, Test and Verification Solutions Tutorial

T7: Easier UVM – Making Verification Methodology More Productive

John Aynsley, Doulos, United Kingdom Tutorial

T8: The How To’s of Metric Driven Verification to Maximize Verification Productivity

John Brennan, Cadence, United States Matt Graham, Cadence, Canada Tutorial

T9: Creating Portable Tests with a Graph-Based Test Specification

Holger Horbach, IBM, Germany Frederic Krampac, Breker, France Staffan Berg, Mentor Graphics, Sweden Tutorial

T10: Attack Your SoC Power Challenges with Virtual Prototyping

Stefan Thiel, Synopsys, Germany Tutorial

T11: Algorithm Verification with Open Source and SystemVerilog

Daniel Ciupitu, AMIQ Consulting, Romania Andra Socianu, AMIQ Consulting, Romania Tutorial

T12: Revolutionary Debug Techniques to Improve Verification Productivity

Nadav Chazan, Cadence, Israel Tutorial

T13: Architecting SystemVerilog UVM Testbenches for Simulation and Emulation Reuse to Boost Block-to-System Verification Productivity

Hans van der Schoot, Mentor Graphics, United States Ellie Burns, Mentor Graphics, United States Tutorial

T14: Extending Proven Digital Verification Techniques for Mixed-Signal SoCs with VCS AMS

Helene Thibieroz, Synopsys, United States Adiel Khan, Synopsys, United Kingdom Pierluigi Daglio, STMicroelectronics, Italy Gernot Koch, Micronas, Germany Tutorial

Presentation & Papers

Session T1: Analog/Mixed-Signal Design and Verification

T1.1: Accelerated SOC Verification Using UVM Methodology for a Mix-signal Low Power Design Giuseppe Scata, Ashwini Padoor – Texas Instruments Vladimir Milosevic – ELSYS Eastern Europe Slides Paper
T1.2: A Framework for AMS Verification IP Development with SystemVerilog, UVM and Verilog-AMS Jeganath Gandhi Rajamohan, Mike Bartley – Test and Verification Solutions Slides Paper
T1.3: UVM Ready: Transitioning Mixed-Signal Verification Environments to Universal Verification Methodology Arthur Freitas, Regis Santonja – Freescale Semiconductor Slides Paper
T1.4: NVVM: A Netlist-Based Verilog Verification Methodology for Mixed-Signal Design Jiping Qiu, Kurt Schwartz – Texas Instruments Slides Paper

Session T2: Advanced Verification

T2.1: Implementation of a Closed Loop CDC Verification Methodology Andrew Cunningham, Ireneusz Sobanski – Intel Slides Paper
T2.2: A Pragmatic Approach to Meta-Stability Aware Simulation Joseph Bulone – Kalray Roger Sabbagh – Mentor Graphics Slides Paper
T2.3: The Universal Translator – A Fundamental UVM Component for Networking Protocols David Cornfield – AppliedMicro Slides Paper
T2.4: Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM Verification Roman Wang – Advanced Micro Devices Mike Bartley, Suresh Babu – Test and Verification Solutions Slides Paper

Session T3: IP Reuse & Design Automation

T3.1: A Meta-Modeling-Based Approach for Automatic Generation of Fault-Injection Processes Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker – Infineon Technologies and Technische Universität München Thomas Kruse – Infineon Technologies Slides Paper
T3.2: A Methodology for Vertical Reuse of Functional Verification from Subsystem to SoC level with Seamless SoC Emulation Testing Pranav Kumar, Digvijay Pratap Singh – STMicroelectronics Ankur Jain – Mentor Graphics Slides Paper
T3.3: A Real World Application of IP-XACT for IP Packaging – Bridging the Usability Gap Philip Todd – Dialog Semiconductor Slides Paper
T3.4: Generation of UVM Compliant Test Benches for Automotive Systems Using IP-XACT with UVM-SystemC and SystemC AMS Extensions Ronan Lucas, Emmanuel Vaumorin – Magillem Philippe Cuenot – Continental Yao Li, Zhi Wang, Marie-Minerve Louërat, Jean-Paul Chaput, François Pecheux, Ramy Iskander – Université Pierre et Marie Currie / LIP6 Martin Barnasconi – NXP Semiconductors Thilo Vörtler and Karsten Einwich – Fraunhofer IIS/EAS Slides Paper

Session T4: System Level Design & Verification

T4.1: VP Performance Optimization Rocco Jonack, Juan Lara Ambel – Intel Slides Paper
T4.2: Simulation and Debug of Mixed Signal Virtual Platforms Enabling Hardware-Software Co-Development Vincent Motel, Alexandre Roybier, Serge Imbert – Cadence Design Systems Slides Paper
T4.3: UVM-SystemC based Hardware in the Loop Simulations for Accelerated Co-Verification Paul Ehrlich, Thilo Vörtler – Fraunhofer IIS/EAS Thang Nguyen – Infineon Technologies Slides Paper
T4.4: CRAVE 2.0: The Next Generation Constrained Random Stimuli Generator for SystemC Hoang M. Le – University of Bremen Rolf Drechsler – University of Bremen and DFKI GmbH Slides Paper
T4.5: Enriching UVM in SystemC with AMS Extensions for Randomization and Coverage Thilo Vörtler, Karsten Einwich – Fraunhofer IIS/EAS Yao Li, Zhi Wang, Marie-Minerve Louërat, Jean-Paul Chaput, François Pecheux, Ramy Iskander – Université Pierre et Marie Currie / LIP6 Martin Barnasconi – NXP Semiconductors Slides Paper


T5.1: The Top Most SystemVerilog and UVM Constrained Random Gotchas Ahmed Yehia, Gabriel Chidolue – Mentor Graphics Slides Paper
T5.2: Versatile UVM Scoreboarding Jacob Sander Andersen, Peter Jensen, Kevin Steffensen – Syosil Slides Paper
T5.3: Reboot your Reset Methodology: Resetting Anytime with the UVM Reset Package Courtney Schmitt – Analog Devices Phu Huynh, Stephanie McInnis, Uwe Simm – Cadence Design Systems Slides Paper
T5.4: Connecting a Company’s Verification Methodology to Standard Concepts of UVM Frank Poppen – OFFIS Marco Trunzer, Jan-Hendrik Oetjens – Robert Bosch Slides Paper
T5.5: Introduction to Next Generation Verification Language – Vlang Puneet Goel – Coverify Sumit Adhikari – NXP Semiconductors Slides Paper

Session T6: Low Power Methodologies

T6.1: Combining Static and Dynamic Low Power Verification for the Power-Aware SoC Sign-off Himanshu Bhatt, Prashant Mallikarjun, Adiel Khan – Synopsys Slides Paper
T6.2: Complex Low Power Verification Challenges in NextGen SoCs: Taming the Beast! Abhinav Nawal, Gaurav Jain, Joachim Geishauser – Freescale Semiconductor Slides Paper
T6.3: Power Aware Models: Overcoming Barriers in Power Aware Simulation Mohit Jain, J.S.S.S. Bharath, Amit Singh, Vishal Bhimani – STMicroelectronics Amit Srivastava, Bharti Jain – Mentor Graphics Slides Paper

Session T7: Verification Management

T7.1: Connecting Enterprise Applications to Metric Driven Verification Matt Graham, John Brennan – Cadence Design Systems Gergely Sass – NXP Semiconductors Slides Paper
T7.2: Requirements-driven Verification Methodology (for Standards Compliance) Serrie Chapman, Mike Bartley – Test and Verification Solutions Slides Paper

Posters & Papers

Analog/Mixed-Signal Design & Verification

P1.1: Power-Aware Verification in Mixed-Signal Simulation Atul Pandey – Mentor Graphics Mattias Welponer, Gregor Kowalczyk – Infineon Technologies Poster Paper
P1.2: With Great Power Comes Great Responsibility: A Method to Verify PMIC’s Using UVM-MS Dor Spigel, Moshik Hershcovitch – Microsemi Poster Paper

Advanced Verification

P2.1: A Guide to Using Continuous Integration within the Verification Environment Jason Sprott, André Winkelmann, Gordon McGregor – Verilab Poster Paper
P2.2: An Effective Design and Verification Methodology for Digital PLL Biju Viswanathan, Rajagopal P C, Jobin Cyriac, Ramya Nair, Joseph J Vettickatt – Network Systems and Technologies Poster Paper
P2.3: Data Path Verification on Cross-domain with Formal Scoreboard Liu Jun – Intel Poster Paper
P2.4: OSVVM: Advanced Verification for VHDL Jim Lewis – SynthWorks Poster Paper
P2.5: RTL2RTL Formal Equivalence: Boosting the Design Confidence M Achutha KiranKumar V, Aarti Gupta, Ss Bindumadhava – Intel Poster Paper

IP Reuse & Design Automation

P3.1: Automating Netlist Modifications Required by Functional Safety Harald Lüpken, Dirk Hönike, Michael Rohleder – Freescale Semiconductor Poster Paper
P3.2: Reusable Processor Verification Methodology Based on UVM Mustafa Khairallah – Boost Valley Maged Ghoneima – Ain Shams University Cairo Poster Paper
P3.3: Pedal Faster! Or Make Your Verification Environment More Efficient. You Choose Poster Paper

System Level Design & Verification

P4.1: An Open and Fast Virtual Platform for TriCore-based SoCs Using QEMU Bastian Koppelmann, Bernd Messidat, Markus Becker, Christoph Kuznik – CLAB, University of Paderborn Wolfgang Mueller, Christoph Scheytt, – Heinz Nixdorf Institute, University of Paderborn Poster Paper
P4.2: Understanding the Effectiveness of your System-Level SoC Stimulus Suite Robert Fredieu, Andreas Meyer – Mentor Graphics Alan Hunter – ARM Poster Paper
P4.3: Hardware/Software Co-Simulation of SPI Enabled ASICs and Software Drivers for Fault Injection and Regression Tests Elias Kyrlies-Chrysoulidis, Thomas Guertler, Andreas Plange, Matthias Auerswald – Continental Josef Schmid – iSyst Poster Paper
P4.4: ISO 26262: Better be Safe with Modelling and Simulation on System-Level Joachim Hößler – ikv++ technologies Sven Johr – TWT GmbH Thang Nguyen – Infineon Technologies Stephan Schulz – Fraunhofer IIS/EAS Gert-Jan Tromp – Dizain-Sync Poster Paper

Low Power Methodologies

P6.1: Low Power Verification Methodology Using UPF Query Functions and Bind Checkers Madhur Bhargava, Durgesh Prasad – Mentor Graphics Poster Paper

Verification Management

P7.1: Advancing Traceability and Consistency in Verification and Validation Walter Tibboel, Martin Barnasconi – NXP Semiconductors Poster Paper