27 - 28 October, 2020

Virtual Conference

Event Details

MP Associates, Inc.

WEDNESDAY October 19, 11:30am - 1:00pm | Forum 4

Advanced UVM tips & tricks - tutorial

Srinivasan Venkataramanan - CVC Pvt., Ltd.
Ajeetha Kumari - CVC Pvt., Ltd.
Srinivasan Venkataramanan - CVC Pvt., Ltd.
Ajeetha Kumari - CVC Pvt., Ltd.
Universal Verification Methodology (UVM) is the industry standard verification methodology for Verification using SystemVerilog (SV). UVM provides means of doing verification in a well-defined and structured way. It is a culmination of well-known ideas, thoughts and best practices. It is also supported by a standard set of base classes to help building structured verification environment faster. More details about the standard can be found at: http://www.accellera.org Given the major adoption of UVM across the globe and across the industry, advanced users are looking for tips and tricks to improve their productivity. In this tutorial we will begin with a quick introduction to basic UVM. Then we will present few of the advanced topics in UVM such as Factory, importance of hierarchical names in the UVM environment, Configuration Database use cases, mis-use traps, run time phasing covering both active & passive phasing, phase jumping etc. Though UVM does bring in great deal of modularity and provides flexibility in configuring, overriding transactions and components, such a power comes with its own set of issues – especially when things do not work as expected (on the testbench side as far as UVM and this tutorial is concerned). While the industry has well understood the debug of design issues, debug fn the testbench especially with modern, OOP based components is not that well understood by the community. In this tutorial the authors share their long experience of assisting customers with run time debug of common UVM issues and potential solutions to them. We have included abstract agenda in the PDF, will add more details to make it cohesive and free flowing