29 - 30 October, 2019

Munich, Germany

Event Details

MP Associates, Inc.
THURSDAY October 25, 10:45am - 12:15pm | Forum 4
Cyril Spasevski - Onomia
User experiences from simulations based on Transaction Level Modeling.

1.1Using UVM-ML Library to Enable Reuse of TLM2.0 Models in UVM Test Benches
As new IC process technologies are deployed, with decreasing geometrical dimensions, rapid progress is made in enabling integration of more transistors on a single chip. This enables hardware designers to implement more complex hardware architectures. Nowadays, a lot of the data processing algorithms are implemented in specialized HW instead of SW. The design flow usually starts with an early reference models development to explore different aspects of the algorithms. The verification task is also becoming more challenging as the complexity of the design increases. ASIC verifiers can reuse the reference models in their TBs to check the functional correctness of the algorithm implementation. TLM models are a natural fit to use with UVM TBs. The integration of TLM models into UVM-TBs can be easily accomplished by using UVM-ML library, which enables the communication between UVM-SV and TLM/SC. Our work provides an industrial case study that answers practical UVM-ML deployment questions.
 Speaker: Sarmad J. Dahir - Cadence Design Systems,GmbH
 Authors: Sarmad J. Dahir - Cadence Design Systems,GmbH
Hans-Martin Bluethgen - Cadence Design Systems,GmbH
Rafael Zuralski - Cadence Design Systems,GmbH
Nils Luetke-Steinhorst - Cadence Design Systems,GmbH
Christian Sauer - Cadence Design Systems,GmbH
1.2Acceleration of Product and Test Environment Development using SystemC-TLM.
While SystemC/TLM-2.0 is an established technology allowing the parallel development of both hardware and software components of a platform or product, less emphasis has been placed on the ability to use the same technology to develop test environments. Test Environments have become increasingly complex, tracking the complexity of products; they have become products in their own right. This paper demonstrates the benefits of using SystemC-TLM Virtual Platforms for preparing test sequences before having real hardware. The proposed approach involves two software-based virtual platforms: for the product and the test equipment. Specific libraries and drivers have been developed for TestStand (National Instrument’s test sequence manager) allowing communication with a SystemC/TLM virtual platform modelling the test equipment. Early results already show the expected benefit of the individual Virtual Platforms, finding bugs early in firmware for instance, and show an overall acceleration of test development of several weeks.
 Speaker: Florian Barrau - Schneider Electric
 Authors: Florian Barrau - Schneider Electric
Alexandre Piccini - Schneider Electric
Mark Burton - GreenSocs Ltd
Luc Michel - GreenSocs Ltd
Alexandre Nabais Moreno - Schneider Electric
Clement Deschamps - GreenSocs Ltd
1.3Performance Modeling and Timing Verification for DRAM Memory Subsystems
Contemporary System-on-Chips comprise multiple processing elements competing for resources, most of all memory bandwidth. It is undisputed that orchestrating the memory accesses in a SoC is one of the biggest challenges today. Due to the high complexity designers often resort to emulation using dedicated hardware for identifying performance issues. An alternative are abstract models trading accuracy for simulation speed. This approach has many obvious advantages, but is often not applicable, because the required simulation-IPs are not available and development would take too much time. We address this issue by providing a framework for modeling and verification of DRAM memory subsystems based on SystemC and the Approximately-Timed (AT) coding style of TLM2.0. The models achieve a speed-up of 100x compared to RTL. Timing accuracy, in terms of simulation time and average latency, is in a pessimistic corridor of 0-15%. We present our modeling approach, verification environment, and achieved results.
 Speaker: Thomas Schuster - Cadence Design Systems,GmbH
 Authors: Thomas Schuster - Cadence Design Systems,GmbH
Peter Prueller - Cadence Design Systems,GmbH
Christian Sauer - Cadence Design Systems,GmbH