Petri Solanti - Mentor, A Siemens Business
The algorithms needed to teach a computer to “see, understand and make decisions” for ADAS and Autonomous Drive systems require a significant amount of parallel compute performance executing at the lowest possible power. Often the technology used to implement these functions employs Deep Neural Networks that demand even more high-performance parallel compute resources and inference solutions that are also low power. FPGAs and ASICs can meet these requirements for acceleration and power, but RTL development takes too long and does not adapt to rapid algorithm and late specification changes that frequently occur. To fully test these algorithms and systems thousands of driving scenarios and design parameters are required to simulate both the hardware and software to ensure safety.
This tutorial presents how High-Level Synthesis (HLS) helps designers take their algorithms and/or trained neural networks and rapidly generate low-power, high performance custom hardware accelerators. Using hardware emulation in the loop, the hardware accelerators can be verified for functional correctness, performance and power, and plugged into a larger heterogeneous system of hardware and software running on multiple ECUs. This enables the co-development of AUTOSAR software, ECU hardware and high-performance vision/networking accelerators together with mechanical system actuators, sensors and traffic scenarios.
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