THURSDAY October 25, 3:15pm - 4:45pm | Forum 6
EVENT TYPE: REGULAR SESSION
SESSION 11Advanced Verification Techniques
Raik Brinkmann - OneSpin Solutions GmbH
Advanced Approaches to solve unusual Verification Problems.
|11.1||Use of Formal Methods for Verification and Optimization of Fault Lists in the Scope of ISO26262|
|This work aims at an alternative method to verify the correctness of Fault Lists generated by tools during ISO26262 Fault Injection Simulations. The lists generated by simulation tools are verified against lists from formal tools. The evaluation between the lists allows a higher Tool Confidence Level (TCL), important for ISO26262 Tool Qualification. In addition, formal tools have the potential of performing optimization in Fault Lists by annotation of the expected behavior of the design under fault. Our work demonstrates the feasibility of using Formal Methods to verify and optimize the fault list from simulators. Results indicate an average reduction of 29.5% on the number of faults to be simulated and demonstrate that it is possible to increase TCL by verification of the fault lists.|
|Speaker:||Felipe A. da Silva - Cadence Design Systems,GmbH & Delft Univ. of Technology
|Authors:||Felipe A. da Silva - Cadence Design Systems,GmbH & Delft Univ. of Technology
Ahmet Cagri Bagbaba - Cadence Design Systems,GmbH
Said Hamdioui - Delft Univ. of Technology
Christian Sauer - Cadence Design Systems,GmbH
|11.2||Formal Verification of a Highly Configurable DDR Controller IP|
|In this paper, we describe the formal verification methodology used for the AMBA AXI Port Interface (XPI) controller of the Synopsys DesignWare Cores DDR Memory Controller . The controller is feature-rich and the XPI is a highly configurable design, which varies with both hardware and software configuration parameter settings. This creates a formidable challenge for traditional verification methods as there are many combinations of settings resulting in long simulation cycles to reach the coverage objectives. Contrast this with formal verification, which uses mathematical algorithms to efficiently test design behaviors for all possible stimulus and configurations. We will describe the formal verification flow including configurable formal testbench implementation and formal coverage closure.|
|Speakers:||Sumit Neb - Synopsys, Inc.
Roger Sabbagh - Oski Technology, Inc.
|Authors:||Sumit Neb - Synopsys, Inc.
Chirag Agarwal - Oski Technology, Inc.
Deepak K. Gupta - Oski Technology, Inc.
Roger Sabbagh - Oski Technology, Inc.
|11.3||Fault Effect Propagation using Verilog-A for Analog Test Coverage|
|In today’s small size transistors technologies, transistors become more susceptible to defects that occur either due to process variations or defects like open and short circuits during the manufacturing process. To evaluate the quality of the IC test, Analog test coverage is essential, although it is computationally expensive. Performing system level ADS with several complex analog blocks at the transistor level is time-consuming. One possibility to reduce ADS time is to use behavioral models for circuit blocks where defects are not being injected. Yet, the models should be able to propagate the defects responses to the observation point (a pad). A methodology for augmenting fault effects to the Verilog-A behavior models of analog circuits using Look-Up Tables (LUT) is presented in this paper. System level ADS is performed where analog blocks replaced with their behavior models. This speeds up the simulation of faults in analog circuits.|
|Speaker:||Ahmed Sokar - Infineon Technologies AG
|Authors:||Aishwarya Prabhakaran - Infineon Technologies AG
Ahmed Sokar - Infineon Technologies AG
Jaafar Mejri - Infineon Technologies AG