29 - 30 October, 2019

Munich, Germany

Event Details

MP Associates, Inc.
THURSDAY October 25, 3:15pm - 4:45pm | Forum 7
EVENT TYPE: REGULAR SESSION
SESSION 12
AMS Verification
Chair:
Karsten Einwich - COSEDA Technologies
User Experiences on AMS Verification.

12.1Using Constraints for SystemC AMS Design and Verification
In this paper we discuss how constraints can be applied for the design and verification of mixed-signal virtual prototypes based on SystemC AMS[1][2]. We show that the CRAVE constraint solver has been extended to handle real value constraints for analog systems. Furthermore, we explain how constraints can be easily used to modify the DUT for modeling parameters and other kinds of variations. In an example we show how our flow can be used to modify the DUT based on constraints and to generate random stimuli to verify for verification with UVM-SystemC.
 Speaker: Thilo Vörtler - COSEDA Technologies
 Authors: Thilo Vörtler - COSEDA Technologies
Karsten Einwich - COSEDA Technologies
Muhammad Hassan - DFKI
Daniel Grosse - University of Bremen & DFKI GmbH
12.2Methodology for Automated Generation and Validation of Analog Behavioral Models for Mixed-Signal Verification
As the complexity of mixed-signal SoC designs keeps growing nowadays, top-level simulation is inevitable to guarantee the correct functionality. While the high accuracy of SPICE-models is not necessary for top-level verification, they are replaced with analog behavioral models to accelerate the top-level simulation. However, the creation and validation of analog behavioral models still imply much manual work. As a real number model shows advantages in simulation speed and digital integration, we propose an approach in this paper to generate real number models of analog components based on the Infineon’s meta-modeling concept. Meanwhile, the automation of UVM-MS testbench generation for model validation is also presented in this paper.
 Speaker: Nan Ni - Infineon Technologies AG
 Authors: Nan Ni - Infineon Technologies AG
Chunya Xu - Infineon Technologies AG
Sebastian Simon - Infineon Technologies
12.3Protocol Verification of an IEEE 802.3bw PHY
IEEE 802.3bw-2015 (PHY) specifies the physical layer of automotive ethernet which drives a single balanced twisted-pair medium (100BASE-T1). The PHY implementation requires analog/mixed signal circuits, pulling verification into the mixed signal domain. PHY verification cannot be completed with a common UVM test environment due to the analog circuits involved. Still a single verification environment is desired, this yields less time spent in test development and improved communication between engineers, resulting in faster time to market with better verification quality and less development cost. The problem of combining digital and analog circuits in a single UVM verification environment is addressed by introducing dedicated UVM mixed signal extensions. The application of the verification environment is demonstrated by verifying the PHY, which is part of an Automotive Ethernet system.
 Speaker: Joen C. Westendorp - NXP Semiconductors
 Authors: Joen C. Westendorp - NXP Semiconductors
Marcel Oosterhuis - NXP Semiconductors