Event Details

MP Associates, Inc.
WEDNESDAY October 24, 2:15pm - 3:45pm | Forum 7
Tutorial 12 - Requirements Driven Design Verification Flow

Ateş Berna - ElectraIC
Ahmet Jorganxhi - ElectraIC
Ateş Berna - ElectraIC
The purpose of this tutorial is to describe verification process flow especially to be used in safety critical ASIC/FPGA designs. Verification of a design consist of two main goals. First one is to verify if the design behaves as described in the requirements. In this process of verification, each requirement is tested and full legal input space is explored. The second goal is to ensure that design does not do anything it is not supposed to do. In general, this process of verification makes sure that every component is tested and illegal conditions are handled. Test scenarios needs to be defined in a Verification Procedure Document. It is important and crucial that Verification Procedure Document verifies all defined requirements, since in a safety critical design (i.e. DO-254, ISO 26262) everything is about tracing all verification activity back to requirements. Therefore, by using a requirements tracing tool like ReqTracer of Mentor Graphics, Requirements and Verification Procedure documents are linked together and is made sure that current test scenarios are verifying all RTL design requirements. Once test scenarios are determined, the next step is to create the verification environment. In this tutorial, design will be verified through Universal Verification Methodology (UVM) and as verification language SystemVerilog is used. After verification environment is created, the next step is to implement test cases. Each test scenario verifies certain requirements. Therefore, it is important to make sure that test case irreproachably verifies corresponding requirements. 
In this tutorial verification of requirements with assertions and self-checking mechanism is explained. Self-checking is a mechanism developed by ElectraIC to be used especially in safety critical design verifications. Assertions are used in verification of the occurrence of specific conditions or sequence of events and it is important to be ensured that each assertion correctly is triggered under required conditions and verifies functionality as explained in the corresponding requirement. Due to this reason, each assertion is verified with SVA Unit and is made certain that all assertions operate properly. Test Case simulation results must be supported by functional coverage and code coverage analysis results. Functional coverage is used for design functionality verification and is explicitly defined in the form of a functional coverage model that is composed of assertions and 'cover points’, which have certain conditions such as ranges, defined transitions or crosses defined in form of 'bins'. On the other hand code coverage analysis is used to measure test scenario effectiveness and is composed of statement, branch, expression, FSM and toggle coverage analysis. Advanced RTL analysis (linting and structural RTL analysis) is another way to find possible problems in the design. HDL linting, including structural static analysis, improves the quality of RTL and reduces risk earlier in the design cycle, allowing the design to be signed-off with confidence. Therefore, using RTL analysis early in the RTL development phase improves QoR of RTL, accelerates IP verification, decreases development time, and increases productivity to help meet time-to-market deadlines. 
In conclusion, this tutorial aims to provide many processes/methods/methodologies of advanced verification in a requirements driven design verification flow.

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