29 - 30 October, 2019

Holiday Inn Munich City Centre

Munich, Germany

Event Details

MP Associates, Inc.

WEDNESDAY October 24, 4:00pm - 5:30pm | Forum 6

Tutorial 15 - Unifying Mixed-Signal and Low-Power Verification

Kawe Fotouhi - Cadence Design Systems, Inc.
Andre Baguenier - Cadence Design Systems, Inc.
Adam Sherer - Cadence Design Systems, Inc.

Unifying Mixed-Signal and Low-Power Verification Electronics design has long included digital, analog, and power. It’s enabled us to create the phenomenal array of devices that permeate our lives. More than ever, these design elements are unified on a single chip and the system depends on their integrated functionality. Achieving the performance, quality, and safety metrics needed for commercial and safety-dependent applications will require new technologies and methodologies. Often, a tutorial with a title such as this one professes a single, grand-unification methodology but doing so for mixed-signal and low-power at this time isn’t credible. The electronics industry is driving innovation in both the standards and in IC development space because of the complexity of the problem. While that is happening, we need to get ICs built, verified, and in production so we have a series of immediate challenges we need to address.

As we work on these topics, a general methodology may emerge and along the way we will make each project more efficient with solutions to these challenges. As sample of such challenges includes the following:
• Connectivity verification
• Early/system verification for mixed-signal
• Fast build-time for mixed-signal simulation
• Fast SoC/full-chip simulation
• Mixed-signal and low-power verification
• Mixed-signal coverage reporting and analysis
• Simulation of analog trims
• Testbench-driven (UVM) mixed-signal simulation

The challenges in the list above cover a wide range of topics. From tool level topics to methodology topics, from system level to transistor level. The tutorial will address each of these in general, and then select 3 – 4 topics for an in-depth discussion. For the detailed discussions, we will present an open-source reference design to support a cookbook approach to addressing each challenge. And standards like Accellera SystemVerilog-AMS, IEEE-1800, Accellera UPF, and IEEE-1801 play an important role in realizing those devices. However, the next generation of devices will require higher performance, more sophisticated power management, higher abstraction, and more. We need to examine the content and application of the Accellera and IEEE standards that enable these mixed signal, low power SoCs to ensure that we are enabling interoperability and defining the requirements for the next generation of electronics. Attendees to this tutorial will gain practical knowledge they can apply to the development of designs with mixed-signal and low power requirements. These topics, and others that attendees will certainly suggest in this interactive tutorial, will provide the stepping stones the semiconductor industry needs to develop a unifying methodology for mixed-signal and low-power.

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