THURSDAY October 25, 10:45am - 12:15pm | Forum 5
EVENT TYPE: REGULAR SESSION
Mark Burton - GreenSocs SAS
New twists on SystemC.
|2.1||Hardware Construction with SystemC|
|Hardware construction is a structural design approach that involves algorithmic generation of circuit netlist using high-level programming language. Languages that support this approach are known as hardware construction languages (HCL). Among the best-known HCLs are Chisel and Bluespec, adopted both in industry and in academia. On the other side, C++ and SystemC are known in context of high-level synthesis (HLS), a process that involves automatic transformation of untimed behavioral models into RTL. Clearly, these two approaches are complimentary and can be potentially implemented in a single language and synthesis flow. We explored opportunity to bring hardware construction support to SystemC, identified missing pieces in library and tools, and implemented a robust elaboration tool that supports full power of C++ language for synthesizable designs.|
|Speaker:||Roman Popov - Intel Corp.
|Authors:||Roman Popov - Intel Corp.
Mikhail Moiseev - Intel Corp.
|2.2||Increasing Efficiency and Reuse in Modeling SystemC/TLM IPs Targeting Virtual Prototypes for Software Development|
|High-level hardware description languages like SystemC allow the development of IP models on a high abstraction level, rendering them useful for development of Virtual Prototypes. The Transaction Level Modeling (TLM) open standard offers a base protocol with defined interfaces for interoperability and compatibility with different IP. In our work we demonstrate how far simulation models for peripheral IPs targeting software development can be automatically generated. Moreover, we discuss abstraction methods for modeling IP-specific behavior. The presented techniques are detailed on the example of a USB3.1 host controller and device model. Measurements show that across the modelled IPs approximately 85% of the required code can be automatically generated and reused, resulting in a considerable modeling efficiency increase.|
|Speaker:||David Spieker - Cadence Design Systems,GmbH
|Authors:||David Spieker - Cadence Design Systems,GmbH
Thomas Schuster - Cadence Design Systems,GmbH
Rafael Zuralski - Cadence Design Systems,GmbH
Christian Sauer - Cadence Design Systems,GmbH
|2.3||A Hybrid Channel for Co-Simulation of Behavioral SystemC IP with its Full System Prototype on FPGA|
|This is a report on experience, using a bidirectional asynchronous channel between a SystemC device model and a physical, full system prototype of the same device on FPGA. The asynchronous channel uses TCP sockets when the SystemC model is on a different host, and shared memory when the model is on the same host. Synchronization is maintained between the two sides by aligning the SystemC side with the real-time clock (using Realtimify). The full system is used to co-simulate a complete firewall application, consisting of a NoC firewall module (the DUT), drivers, OS, and application software running on an ARM v7 Zedboard. The asynchronous channel has good performance, especially for shared memory communication, with an overhead in the msec range. Overall simulation speed is sufficient such that real-time performance characteristics can be verified.|
|Speaker:||Miltos D. Grammatikakis - Technological Educational Institute of Crete
|Authors:||Antonis Papagrigoriou - Technological Educational Institute of Crete
Miltos D. Grammatikakis - Technological Educational Institute of Crete
Voula Piperaki - Technological Educational Institute of Crete