29 - 30 October, 2019

Munich, Germany

Event Details

MP Associates, Inc.
THURSDAY October 25, 10:45am - 12:15pm | Forum 7
EVENT TYPE: REGULAR SESSION
SESSION 4
New Horizons in Functional Verification
Chair:
Harry Foster - Mentor, A Siemens Business
How Engineers are tackling the Verification Problems of tomorrow's SOCs.

4.1Advanced Techniques to Accomplish Power Aware CDC Verification
Reduced power is achieved by partitioning SoC into power domains and controlling these by switching off power selectively or reducing voltage levels. Connections across power-domains need to be managed and designers add Isolation cells, Retention logic, and Voltage shifters at power-domain interfaces. Presence of power components challenge CDC-verification and the UPF intent must be incorporated. In this paper we present 4 key challenges posed by low power design on CDC paths and way to overcome them by advanced PA CDC verification techniques and a systematic methodology. Key challenges resolved are: 1. Asynchronous isolation enable signal leading to new CDC paths. 2. Glitch prone combo logic due to isolation insertion. 3. Retention Save-Restore logic coming from asynchronous domains 4. DVFS can result in synchronous relations in clock paths becoming asynchronous as they cross different voltage domains and power switches We will present case studies on production designs to illustrate benefits.
 Speaker: Rohit K. Sinha - Intel Technology India Pvt. Ltd & Mentor Graphics (India) Pvt. Ltd.
 Authors: Ashish Hari - Mentor, A Siemens Business
Rohit K. Sinha - Intel Technology India Pvt. Ltd & Mentor Graphics (India) Pvt. Ltd.
Sulabh K. Khare - Mentor, A Siemens Business
4.2Guiding Functional Verification Regression Analysis using Machine Learning and Big Data Methods
This paper addresses the challenge of reducing the debugging effort required to validate the changes between HW model iterations of the same design during the analysis of its regression test failures. It proposes the utilization of clustering machine learning to learn the design good behavior through the passing regression tests. The buggy test can then be detected when it failed the assignment to any of the trained test clusters in the design regression test suite. Our framework utilizes x-means clustering to identify the trace segment, module name as well as design signals which are suspected to be the culprit of the bad behavior tests. Signal selection step is done to decide which design signals should be included during the machine learning feature extraction step to reduce the model complexity. Additionally, Big-Data processing technique, namely, Map-Reduce is used to overcome the challenge of processing huge trace dump resulted from design execution.
 Speaker: Yasmin ElSharnoby - Cairo Univ.
 Authors: Eman El Mandouh - Mentor, A Siemens Business
Laila Maher - Cairo Univ.
Moutaz Ahmed - Cairo Univ.
Laila Maher - Cairo Univ.
Yasmin ElSharnoby - Cairo Univ.
Amr G. Wassal - Cairo Univ.
4.3Hybrid Flow: A Smart Methodology to Migrate from Traditional Low Power Methodology
Traditionally most of the design SoC design companies have adopted merged based low power implementation methodologies but just as the complexity of an SoC demands a well-structured hierarchical approach to design and verification of its functional specification, the complexity of the power management infrastructure for a SoC requires a hybrid methodology. Because of the strict tape-out schedules and dependencies on internal and external IP teams, transitioning from merged to hierarchical and from UPF1.0 to UPF2.0 for the complete SoC design could be of huge risk as there are lots of uncertainties in terms of QoR. In order to mitigate such risk, we adopted a hybrid methodology which ensures complete reliability and smooth transition. Hybrid flow is essentially a mechanism to enable both merged as well as hierarchical UPF based on partitions and also, it enables to use both partition level UPF1.0 and UPF2.0 syntax in the SoC design Flow
 Speaker: Rohit K. Sinha - Intel Technology India Pvt. Ltd & Mentor Graphics (India) Pvt. Ltd.
 Authors: Rohit K. Sinha - Intel Technology India Pvt. Ltd & Mentor Graphics (India) Pvt. Ltd.
Prashanth N - Intel Corp. & Intel Technology India Pvt. Ltd