THURSDAY October 25, 1:15pm - 2:45pm | Forum 4
EVENT TYPE: REGULAR SESSION
SESSION 5Virtual Prototyping
Tim Kogel - Synopsys, Inc.
The latest techniques for Virtual Prototyping.
|5.1||Fast and Furious: Quick Innovation from Idea to Real Prototype|
|Automotive customers are starting to request sensor prototypes to test new algorithms and application possibilities in the early stage of their design. Reacting fast to their requests can ensure design-win for next generations and a prosperous future for Infineon Sense and Control. For this reason, a new methodology allowing a smooth transition from idea to implementation has been implemented and already used on different products. In particular, product models developed during concept and feasibility studies in SystemC are translated automatically into HDL ready to be synthesized into FPGAs for customers prototyping. The generated HDL is firstly automatically validated via co-simulations with SystemC, then the FPGA prototype is tested on laboratory system testbench and finally the measured results are again automatically compared to simulation results. The flow is highly automatized and allow saving time and effort when developing a prototype for the customers, without compromising on performance and reliability.|
|Speaker:||Simone Fontanesi - Infineon Technologies
|Authors:||Simone Fontanesi - Infineon Technologies
Gaetano Formato - Infineon Technologies
Thomas Arndt - COSEDA Technologies
Andrea Monterastelli - Infineon Technologies
|5.2||Temporal Decoupling – Are "Fast" and "Correct" Mutually Exclusive?|
|Temporal decoupling is a crucial virtual platform performance technique – without it, a virtual platform (VP) is destined to be unusably slow for large workloads. But temporal decoupling affects how the components of a VP interact and thus potentially alters the behavior of software running on the VP. Finding the “best” level of decoupling is thus a matter of balancing conflicting requirements. In this paper, we present our experience, measurements, and experiments with temporal decoupling across a wide range of software workloads and processor and hardware interactions, providing insight into the speed-behavior trade-off and the interesting things that can happen.|
|Speaker:||Jakob Engblom - Intel Corp.
|Author:||Jakob Engblom - Intel Corp.
|5.3||Generating Bus Traffic Patterns|
|During the block level verification using SystemVerilog with the UVM methodology  we were required to generate specific traffic patterns for a bus-based protocol requested by the architect (design engineers, system architect, etc.). The root cause was the specification of the traffic pattern, which was ambiguous and could be interpreted differently by the architect and the verification engineers. For improved reusability across verification environments the traffic patterns could instead be accurately expressed by using a domain specific language (DSL). The DSL could then easily be converted into executable code for producing the expected traffic patterns.|
|Speaker:||Jacob Sander S. Andersen - SyoSil ApS
|Authors:||Jacob Sander S. Andersen - SyoSil ApS
Lars Viklund - Axis Communications AB
Kenneth Branth - SyoSil ApS