29 - 30 October, 2019

Munich, Germany

Event Details

MP Associates, Inc.
THURSDAY October 25, 1:15pm - 2:45pm | Forum 5
EVENT TYPE: REGULAR SESSION
SESSION 6
Generating Stimulus
Chair:
Matthias Bauer - Infineon Technologies
Interesting Approaches for Generating Meaningful Stimulus.

6.1Portable Stimulus Driven SystemVerilog/UVM Verification Environment for the Verification of a High-capacity Ethernet Communication Endpoint
The scope of this paper is to present the steps taken and the challenges faced when using Portable Stimulus(PSS) as an abstraction layer on top of a SystemVerilog/UVM verification environment. The goal is the verification of a highly configurable, high-speed, communication endpoint, covering complex network scenarios and system-level corner cases. PSS is used in conjunction with SystemVerilog/UVM to increase verification efficiency by avoiding “scenario flooding” and keep a tight control of the verification space. All stimuli are defined in the test-bench and they are used to construct directed/random scenarios by utilizing a PSS generation model. The flow of the project in this case requires the SV/UVM VE to keep up with the guidelines for reusability while having an architecture that is compliant with the PSS mechanics of scenario generation. The paper addresses the possible issues and good practices discovered while implementing this verification strategy.
 Speaker: Andrei Vintila - AMIQ srl
 Authors: Andrei Vintila - AMIQ srl
Ionut Tolea - AMIQ srl
6.2Use Stimulus Domain for Systematic Exploration of Time Dimension and Automatic Testcase Construction
The state-of-the-art metric-driven constraint random verification methodology requires achieving full functional coverage as one of its most important metrics. However, defining functional coverage is a subjective and dependent process largely based on human intellects. In this paper, we propose a new concept of Stimulus Domain and use it to explore the stimulation space systematically. As a result, the verification methodology is extended by a stimuli-driven aspect which even overweighs the metric-driven aspect, since the former unfolds the primary source of power of randomization and leads to better functional coverage definition. Furthermore, it can be used for automatic testcase construction while facilitating the reuse of Stimulus Domains across a large set of IPs shared with common functionalities. The proposed approach has been applied to two industrial IPs with its effectiveness proved by around 20 issues identified for legacy feature sets in one case and zero bugs ensured in another case.
 Speaker: Ning Chen - Infineon Technologies AG
 Authors: Ning Chen - Infineon Technologies AG
Martin Ruhwandl - Infineon Technologies AG
6.3MicroTESK: Automated Architecture Validation Suite Generator for Microprocessors
MicroTESK is a tool that automates construction of test program generators for microprocessors. The main part of each generator is the core implementing architecture-independent test generation methods. To produce tests for a specific instruction set architecture, the tool analyzes formal specifications of that architecture and extracts all necessary information, including, first of all, the instructions’ syntax and semantics. The primary use case of the tool is to generate test programs from high-level test templates, or scenarios, provided by verification engineers. In this paper, we present a new facility, namely automatic generation of architecture validation suites, which allows creating simple tests in a “push-button” manner. Such tests exercise individual instructions and short sequences of dependent instructions by applying both random and directed values of the operands. MicroTESK and the underlying approach have been applied to the ARMv8, MIPS64, PowerPC, RISC-V, and x86 architectures.
 Speaker: Alexander Kamkin - Ivannikov Institute for System Programming of the RAS
 Authors: Mikhail Chupilko - Ivannikov Institute for System Programming of the RAS
Alexander Kamkin - Ivannikov Institute for System Programming of the RAS
Alexander Protsenko - Ivannikov Institute for System Programming of the RAS
Sergey Smolov - Ivannikov Institute for System Programming of the RAS
Andrei Tatarnikov - Ivannikov Institute for System Programming of the RAS