27 - 28 October, 2020

Virtual Conference

Event Details

MP Associates, Inc.

WEDNESDAY October 24, 11:45am - 1:15pm | Forum 6

Tutorial 7 - Tutorial on RISC-V Design and Verification

Zdenek Prikryl - Codasip Ltd.
Kevin McDermott - Imperas Software Ltd.
Peter Shields - UltraSoC Technologies Ltd.
Kevin McDermott - Imperas Software Ltd.
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 members building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

Verification requirements not only need to cover the wide range of features and extensions available within the RISC-V standard architecture but also allow for designs with custom instructions. The tutorial will explore the issues and challenges of SoC designers adopting RISC-V from the perspectives of IP Cores, software tools, virtual platforms and on-chip debug analytics for complex multi-core and heterogeneous many-core designs.