THURSDAY October 25, 1:15pm - 2:45pm | Forum 7
EVENT TYPE: REGULAR SESSION
SESSION 8Low Power Design and Verification
Mohammad A. Fahim - Intel Corp.
How people ensure that their SOCs consume less power (and verify it).
|8.1||IEEE 1801 Assisted Custom IP Development and Low Power Checks using Cadence Virtuoso Power Manager|
|Defining and verifying power requirements across analog and digital boundaries involves manual task. The power intent defined at concept level must be considered for development at the IP block level, no matter if these are analog or digital blocks. This makes defining and checking of power intent across these analog and digital hierarchies complicated. Also, the power related checks stop at the analog block boundaries. In order to ease the design process, we applied a new methodology for defining and checking of power intent through nested analog and digital hierarchies. The approach depends on the IEEE 1801 format to define the power intent for both analog and digital sub-blocks.|
|Speaker:||Matthias Steffen - Infineon Technologies AG
|Authors:||Matthias Steffen - Infineon Technologies AG
Amit Chopra - Cadence Design Systems, Inc.
Sonal Singh - Cadence Design Systems, India Pvt. Ltd.
|8.2||A New Approach to Low-power Verification: Low Power Apps|
|The effective verification of low-power designs has been a challenge for many years now. One of the main challenges for the low-power verification engineers has been the fact that there is disconnect between the traditional RTL and low-power objects. Users can not access and manipulate the low-power object in the same way as they do for RTL. Low-power concepts are abstract and the sources which form the low-power information are varied e.g. UPF, HDL and Liberty. The lack of an industry standard in this regard resulted in inconsistency in different ad-hoc approaches adopted by different tool vendors. In this paper we are going to demonstrate with relevant examples and case studies that how UPF 3.0 information model HDL package functions and TCL query functions can be used to do innovative things which are often a very important low power design verification criterion.|
|Speaker:||Abdel Ayari - Mentor, A Siemens Business
|Authors:||Madhur Bhargava - Mentor Graphics (India) Pvt. Ltd.
Awashesh Kumar - Mentor, A Siemens Business
|8.3||UPF Power Models: Empowering the Power Intent Specification|
|Today’s low power SoCs have become incredibly complex involving large number of hard/soft IPs with their own sophisticated power management strategies. As a result, IP integrators must deal with lot of UPF code for the IPs which needs to be integrated in the SoC environment. This causes explosion of power intent code due to hundreds and even thousands of instances of some IPs. Such large amount of power intent code poses several problems in terms of IP integration and functional issues related to power management. This results in costly debug cycles and slow simulations. In this paper, we propose a methodology of expressing the power intent for the IPs based on power models from IEEE 1801 (UPF) in such a way that eases the burden of IP integration and reduces UPF verbosity. The paper demonstrates how power models can be used to address the problems faced by IP integrators.|
|Speaker:||Amit Srivastava - Synopsys, Inc.
|Authors:||Amit Srivastava - Synopsys, Inc.
Harsh Chilwal - Synopsys, Inc.