WEDNESDAY October 30, 10:45am - 12:15pm | Forum 4
EVENT TYPE: REGULAR SESSION
|1.1||A 360 Degree View of Reusability Combatbetween UVM Callbacks and UVM Factory-A Case Study|
|UVM was designed and aimed at standardizing the verification methodologies, which is a consolidation effort from the EDA vendors and Verification community by using best of the features from other commonly and matured methodologies like eRM, VMM and OVM libraries. It has a rich set of features which are aimed at making the test environment and components more reusable and robust. UVM Factory and UVM Callbacks are two amongst the many features which are predominately aimed at making the test bench reusable and more efficient. This paper looks at these two features in depth and makes an attempt to suggest better ways of using them.|
|Speaker:||Vikas Billa - Intel Technology India Pvt. Ltd
|Author:||Vikas Billa - Intel Technology India Pvt. Ltd
|1.2||EURP - Enhanced UVM Register Package|
|The standard UVM register package contains built-in test sequences library which is used to perform most of the basic register and memory tests. These sequences are very useful at IP level verification but at Subsystem/SoC level verification, these sequences take very long time to run. Some limitations in current UVM_REG package like no automatic data checking for memory accesses and limited support for memory burst operation were also seen. In this paper, we are describing how we addressed the above mentioned issues. We are accessing processor programmable registers and memories through a standard UVM_REG API. This API can be used to facilitate dumping register access for reuse from IP to SoC, or format outputs for use in ATE test vectors development etc. We also developed our own register/memory sequences to address the Subsystem/SoC level register and memory testing. Customized code is written to enhance the features of standard UVM_REG model.|
|Speaker:||Abhishek Jain - Qualcomm India Pvt. Ltd.
|Author:||Abhishek Jain - Qualcomm India Pvt. Ltd.
|1.3||Random Stimuli Models for UVM RAL|
|In this document we are targeting a problematic topic which become relevant when using UVM RAL. In general, it is difficult to randomize the registers inside a UVM RAL instance using constraints. Verification engineers typically implement small stimuli models which is randomized and then apply them to the UVM RAL registers afterwards. These models are almost identical to the register model except they can be randomized independently of the register model and constraints can be easier applied. The stimuli models can be generated since the register model and the stimuli model are almost similar and the meta data used for generating the UVM RAL model contains enough information to also allow generation of the related stimuli model. This document presents a generalization of these small stimuli models based on some base classes. The reader is assumed to have basic knowledge on UVM RAL|
|Speaker:||Jacob Sander S. Andersen - SyoSil ApS
|Authors:||Jacob Sander S. Andersen - SyoSil ApS
Laura Montero - SyoSil ApS
Lars Viklund - Axis Communications AB