27 - 28 October, 2020

Holiday Inn Munich City Centre

Munich, Germany

Event Details

MP Associates, Inc.
TUESDAY October 29, 14:15 - 15:45 | Forum 5
EVENT TYPE: TUTORIAL
SESSION 10T
Tutorial 10: RISC-V Integrity: A Guide for Developers and Integrators
Chair:
Ola Dahl - Ericsson
Speaker:
Nicolae Tusinschi - OneSpin Solutions GmbH
Organizer:
Tom Anderson - OneSpin Solutions GmbH

RISC-V is changing the game for IP providers and SoC designers. Providers can offer commercial cores without the need to acquire expensive rights, while open-source implementations are already available. SoC teams that want to use RISC-V processors have several choices today, with even more options expected soon. The sheer number of companies and products using RISC-V guarantees a rich ecosystem and a good opportunity for industry disruption.

However, design integrity is a challenge for both core developers and core integrators. To be successful, IP vendors must produce products that compete against long-established processor families with decades of proven silicon. RISC-V cores must be thoroughly verified as functionally correct using third-party solutions so that different cores all satisfy the Instruction Set Architecture (ISA) and other requirements. Integrators must be certain that available cores are fully compliant, and many will want to re-verify the one they choose.

Verifying that a RISC-V core meets the ISA and does what it is supposed to do is only one aspect of integrity. It is also critical to prove that the core does not do anything that it is not supposed to do. Hardware Trojans or other unintended logic can be inserted at multiple points in the development process. Showing that the RISC-V core can be trusted requires proving that no such issues exist. Only formal verification has the potential to prove both ISA compliance and trust.

Trojans can be used by malicious agents to compromise a chip during operation, but some types of unintentional design errors can also provide an attack gateway. Analysis of the RISC-V core can prove that no such vulnerabilities exist and that the design is secure. Safety must also be addressed since many RISC-V designs are used in safety-critical applications. Standards such as ISO 26262 place demanding requirements on chip designs so that they will continue to function even in the presence of random errors such as Alpha particle hits.

This tutorial provides guidance for RISC-V core vendors who need to verify their IP, developers of cores for internal consumption, engineers evaluating cores for possible use, and SoC teams integrating RISC-V cores from internal or external sources. It covers the complete scope of RISC-V core and SoC integrity: functional correctness (compliance to the ISA), safety, security, and trust. It includes examples of actual bugs found in open-source implementations of RISC-V cores and RISC-V-based SoCs.


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