WEDNESDAY October 30, 3:15pm - 4:45pm | Forum 7
EVENT TYPE: REGULAR SESSION
SESSION 12Advanced Verification 2
|12.1||Unified Test Writing Framework for Pre and Post Silicon Verification|
|Day by day there is an increasing need of integrating/reusing the infrastructure across all the stages of product development right from pre-silicon design verification to post-silicon test validation, evaluation and applications board validation. We propose a framework, built on UVM centric digital verification environment that not only enables analog designers/test writers to write tests without having to know the complexities of the underlying UVM but also opens up a common communication medium over which the design, test, evaluation and application can talk and exchange tests/high level functions. This framework is generic and can be used by any project as most of the infrastructure needed is being dumped from IP-XACT by custom generators.|
|Speaker:||Rahulkumar Patel - Analog Devices, Inc.
|Authors:||Rahulkumar Patel - Analog Devices, Inc.
Pablo Cholbi - Analog Devices, Inc.
Sivasubrahmanya Evani - Analog Devices, Inc.
Raman K - Analog Devices, Inc.
|12.2||Processing Deliberate Verification Errors During Regression Quis Custodiet Ipsos Custodes / Who Will Check the Checkers?|
|This paper describes a tool flow methodology, based upon Cadence® vManagerTM, intended to improve both the quality of Design Verification (DV) and automation of its regression. It proposes a methodology in which special tests may be written, which will check the checkers, and then can be fully included in all the DV regression of the project. The DV of the project therefore becomes twofold: to check that the design is fully verified and the checkers themselves are fully functional. This paper focuses on the regression analysis flow automation for special tests, based upon industry standards, like SystemVerilog and UVM.|
|Speaker:||Alastair Lefley - ams AG
|Authors:||Alastair Lefley - ams AG
Roger Witlox - ams AG
Clemens Süßmuth - ams AG
Thomas Ziller - Cadence Design Systems,GmbH
Kawe Fotouhi - Cadence Design Systems,GmbH
|12.3||Don’t Forget the Protocol! A CDC Protocol Methodology to Avoid Bugs in Silicon|
|Designers add synchronization logic to prevent the propagation of metastable events, but often times, designers do not implement or verify the correct CDC protocol. Without a correctly implemented protocol, a CDC structure will not function correctly and thus, lose or corrupt data or experience metastability. In this paper, we will discuss the difficulties encountered with current CDC protocol verification methodologies and present a complete methodology to overcome the current challenges.|
|Speaker:||Abdelouahab Ayari - Mentor, A Siemens Business
|Authors:||Abdelouahab Ayari - Mentor, A Siemens Business
Sukriti Bisht - Mentor, A Siemens Business
Sulabh K. Khare - Mentor, A Siemens Business
Ashish Hari - Mentor, A Siemens Business
Kurt Takara - Mentor, A Siemens Business