Kawe Fotouhi - Cadence Design Systems,GmbH
In today’s SoC designs, the level of interaction between analog structures and digital logic is increasing dramatically. The pure “divide-and-conquer” approach to design and verification has proven not to be enough anymore. The analog/digital interdependency creates a requirement for a more integrated and sophisticated approach to mixed-signal verification.
For good reasons, mixed-signal verification teams are working in different environments and domains:
- The pure analog verification is based on transistor-level circuits being designed as schematics and simulated within the analog design environment.
- In the digital domain, metric-driven verification based on UVM methodology has become a quasi-standard.
- At the SoC level, you need a way to quickly model your design with enough accuracy for your application. Real number modelling (RNM) allows you to take the best from both worlds.
A predictable verification closure flow requires an efficient planning and metrics management using automated checks and coverage at the block, chip, and system levels simultaneously. New ISO standards like 26262, advanced-node technologies, and the requirements for verification quality, forced industry leaders to seek for a more formalized methodology – including analog.
Cadence provides two domain specific platforms to accomplish verification closure: Cadence® vManager™ platform and the Virtuoso® ADE product suite. In the latest releases, these platforms can synchronize the verification plans and results data in real-time which enables a full qualification of a mixed-signal verification signoff. Cadence vManager™ Metric-Driven Signoff Platform, an automated verification planning and management solution, is the lead tool in the digital flow. The tool deploys execution runs, sets up analysis views, organizes and debugs errors, and generates additional verification scenarios.
Virtuoso® ADE Assembler and Verifier allow users to do analog verification planning, synchronize and check specification values, automate their analog verification, and get a global view of the status of different team members. With the new link to vManager, these analog contributions are an integral part of the chip verification process.
The heart of the verification is communication and planning. The “vplan” is the central document to align the different teams and structure the results. The new connection between ADE Verifier and vManager allows the user to develop the vplan as a joint effort using both tools for all 3 domains: analog, digital and RNM. This capability allows analog and digital engineers to continue to work in their familiar environments while working together on the same plan. The results are accessible in a single cockpit enabling an efficient sign off process and tracking for all domains.
Attendees to this tutorial will gain practical knowledge on how to enable the development of a joint verification plan for the corresponding domains. Furthermore, the tutorial shows how analog and digital verification-execution and verification plan-refinement is done inside ADE Verifier in parallel with vManager. Verification results and the plans are synchronized within the vManager to track the overall verification progress in real-time.
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