WEDNESDAY October 30, 10:45am - 12:15pm | Forum 5
EVENT TYPE: REGULAR SESSION
|2.1||Integrating Parallel SystemC Simulation into Simics® Virtual Platform|
|The SystemC library is widely used to model and simulate system-level designs at an early stage for functional and performance analysis. Simics® is a tool for development and simulation of virtual platforms and is used to enable software development to be done earlier in the product development process. With the introduction of the Simics SystemC Library in Simics 5, it supports IP block, device and subsystem models developed in SystemC. We demonstrate integration of an engine for parallel SystemC simulation, called RISC (Recoding Infrastructure for SystemC), into Simics. We show results exhibiting high speedups using RISC.|
|Speaker:||Daniel M. Mendoza - Intel Corp. & Univ. of California, Irvine
|Authors:||Daniel M. Mendoza - Intel Corp. & Univ. of California, Irvine
Ajit Dingankar - Intel Corp.
Zhongqi Cheng - Univ. of California, Irvine
Rainer Doemer - Univ. of California, Irvine
|2.2||SystemC-to-Verilog Compiler: a Productivity-Focused Tool for Hardware Design in Cycle-Accurate SystemC|
|We present the SystemC-to-Verilog Compiler (SVC) – a tool that translates cycle accurate SystemC to synthesizable Verilog. SVC supports SystemC synthesizable subset in method and thread processes and arbitrary C++ at elaboration phase. SVC produces human-readable Verilog for complex multi-module designs in tens of seconds. The tool performs design checks to detect non-synthesizable code and common coding mistakes. SVC is focused on improving productivity of design and verification engineers, and leaves optimization work for an underlying logic synthesis tool.|
|Speaker:||Mikhail Moiseev - Intel Corp.
|Authors:||Mikhail Moiseev - Intel Corp.
Roman Popov - Intel Corp.
Ilya Klotchkov - Intel Corp.
|2.3||Pythonized SystemC - a Non-Intrusive Scripting Approach|
|Scripting is commonly used in today's applications and EDA tools. For SystemC various proprietary and open source solutions are available. All of them impose various constraints on SystemC users and often restrict the visibility of C++ components to Python. We present a novel approach of integrating SystemC. It does not require any instrumentation or manual preparation and exposes all SystemC types and functions as well as components provided by other libraries, i.e. IP libraries (even in binary form). It allows calling Python from SystemC modules e.g. to implement scriptable components for verification purposes. The paper will outline how this can be used to implement interactive and dynamic tools to assemble Virtual prototypes (VP) easily as well as control their simulation. This is especially useful in HW/SW unit testing and FW verification where the dynamic nature of Python allows to select various test cuts of the VP to ease the tasks.|
|Speaker:||Eyck Jentzsch - MINRES® Technologies GmbH
|Authors:||Eyck Jentzsch - MINRES® Technologies GmbH
Rocco Jonack - MINRES® Technologies GmbH