29 - 30 October, 2019

Holiday Inn Munich City Centre

Munich, Germany

Event Details

MP Associates, Inc.
TUESDAY October 29, 10:00 - 11:30 | Forum 5
Tutorial 2: RISC-V Compliance and Verification Techniques for Processor Cores Including Optional Custom Extensions

Simon Davidmann - Imperas Software Ltd.
Lee Moore - Imperas Software Ltd.
Richard Ho - Google, Inc.
Doug Letcher - Metrics Technology, Inc.
Kevin McDermott - Imperas Software Ltd.

For traditional single or closed sourced instruction set architectures (ISAs), compliance to the ISA specification is addressed during the internal development. With the new, open standard RISC-V ISA, the compliance situation is different. In addition to the multiple IP providers many will also exploit the capability with the open ISA to add custom instructions or other optimizations. Compliance testing therefore has become mission-critical for the RISC-V ecosystem to accommodate the wide adoption and support of compatible features while retaining the optimizations that the ISA permits. For other ISAs compliance testing has been addressed by the processor IP vendor, and as a result methodologies and tools for compliance testing have been kept internal, and are not readily available to the industry in general. Verification of an Open ISA also needs to address the addition of custom instructions and extensions as well as all the standard options and configuration features. The tutorial covers RISC-V Compliance testing and Verification with Instruction stream and cloud based testing.

Part #1 –Imperas This tutorial presentation introduces the methodologies being developed for compliance and verification testing of RISC-V, including a framework for development of additional tests, the development of the tests, reference models, and configurations for the RISC-V specification subsets. Compliance and Verification based on free reference simulator for development and test of hardware including the analysis of the completeness and specification coverage of current compliance tests. Use cases are examined, including testing compliance on various proprietary RTL designs, open source RTL designs, FPGAs, SoCs, ISS models and software tools, with detailed analysis of the issues experienced. This tutorial presentation will answer the key question on what to do on day 1 when you receive a RISC-V implementation – after “Hello World” run the full compliance and verification flow against the Golden Imperas model.

Part #2 - Imperas Introduction and overview of test flow and framework based on a free open source instruction generator for UVM-based RISC-V Processor Verification. Verification based on instruction generator and comparison between RTL under test and a reference simulator. Test results include examples from multiple popular open source processors with detailed reports and highlights.

Part #3 - Metrics The RISC-V Open ISA is different from the established single-sourced ISA in a number of aspects. This tutorial presentation will review the changing role of EDA design flows and addresses the needs of all participants in the SoC IP supply chain to contribute towards the DV task. IP Core providers, open source options, in-house developments, plus options for all participants to modify and extend instructions or extensions – now everyone needs access to verification frameworks. Can cloud based tools help address the expected demand and flexibility for verification capacity?