29 - 30 October, 2019

Holiday Inn Munich City Centre

Munich, Germany

Event Details

MP Associates, Inc.
WEDNESDAY October 30, 10:45am - 12:15pm | Forum 6
EVENT TYPE: REGULAR SESSION
SESSION 3
Generating Stimulus
3.1A Generic Approach for Handling Sideband Signals
This paper outlines a SystemVerilog UVC architecture that enables efficient driving/monitoring of signals that do not belong to any standard protocol (sideband signals). Handling of such signals is a common and time consuming task in any verification environment and hence an efficient sideband UVC can provide many advantages. We first discuss the various requirements that such a UVC should fulfill. These requirements include reusability, genericity, automation, code conciseness, structure and ease of use. We then describe the various UVC architecture features and show how they fulfill the aforementioned requirements. Finally we conclude with the results of this work.
 Speaker: Salman Tanvir - Infineon Technologies
 Authors: Salman Tanvir - Infineon Technologies
Markus Brosch - Infineon Technologies AG
3.2The Powerful Synergy Between UVM and PSS
What value does PSS provide to UVM environments? How does PSS help with UVM coverage maximization? These are two of the most frequently asked questions raised by hardware verification engineers and by UVM users. In this technical paper we analyze several user challenges and compare their UVM model with code snippets of the complementing PSS solution. Most of the session is devoted to the fundamental technical differences and the combined solution. We also discuss the value of applying the solution in terms of automation and thoroughness, as proven in production on actual cutting-edge user designs. This paper provides insights on both PSS and UVM standards and gives valuable information for verification engineers considering PSS for their hardware verification projects.
 Speaker: Sharon Rosenberg - Cadence Design Systems, Inc.
 Author: Sharon Rosenberg - Cadence Design Systems, Inc.
3.3Generic Testbench/Portable Stimulus/Promotability
This paper will discuss the changing landscape of verification caused by the increased importance of software for the success of system-on-chip projects. With software determining an increasing amount of functionality, design teams are adopting software driven verification together with UVM for early bug detection in life cycle. This paper will illustrate the importance of Generic testbench applied to use cases of Subsystem and System-on-chip level verification. Keywords—Generic testbench; Reusability; Portability; Subsytem Verification; System-on-chip Verification I. INTRODUCTION In order to provide a common verification environment across different SoC subsystems and under different platforms (ex: subsystem level simulation, subsystem level emulation, top level simulation) some generic reusable testbench components have been developed. Additionally, a methodology for constructing a testbench and writing reusable tests (reusable across the mentioned platforms) together with examples will be presented with the representative testbench components.
 Speaker: Revati S. Bothe - Sondrel Ltd
 Authors: Revati S. Bothe - Sondrel Ltd
Jesvin Johnson - Sondrel Ltd