29 - 30 October, 2019

Holiday Inn Munich City Centre

Munich, Germany

Event Details

MP Associates, Inc.
TUESDAY October 29, 10:00 - 11:30 | Forum 7
Tutorial 4: Applying Design Patterns to Maximise Verification Reuse @Block, Subsystem and System-on-Chip Level

Revati Bothe - Sondrel Ltd
Jesvin Johnson - Sondrel Ltd
Paul Kaunds - Sondrel Ltd
Verification Planning, Verification Environment development and achieving coverage closure goals on time and under budget are the most challenging assignments in functional verification. In this tutorial, we will provide an in-depth analysis of various planning, implementation, debug and coverage closure challenges faced in functional verification at block level, subsystem and system-on-chip level. By taking relevant examples we will demonstrate how these issues can be either avoided or solved by applying Design Patterns, mainly Environment, Stimulus and Analysis Patterns. We will also highlight some of the benefits like configurability and reusability of UVM and C code.