27 - 28 October, 2020

Virtual Conference

Event Details

MP Associates, Inc.

WEDNESDAY October 30, 13:15 - 14:45 | Forum 4

Andrei Vintila - AMIQ

5.1Results Checking Strategies with the Accellera Portable Test & Stimulus Standard
As at every step in the verification process, whether simulation, emulation, FPGA prototyping or anything else, it is important to ensure that the test generated for the particular target executes as efficiently as possible. The value in PSS is that it is much easier to reuse verification intent across verification/implementation platforms than it is to reuse verification IP across those platforms. The paper will provide a useful explanation of modeling these critical aspects of results checking in an abstract model, discuss how users can tailor their PSS models to provide flexibility to the tools to generate the most efficient tests at different stages throughout the block-to-system verification flow. We will also share results from users who have employed these techniques on actual projects.
 Speaker: Matthew Ballance - Mentor, A Siemens Business
 Authors: Tom Fitzpatrick - Mentor, A Siemens Business
Matthew Ballance - Mentor, A Siemens Business
5.2Portable Stimuli Over UVM, Using Portable Stimuli in HW Verification Flow
In this paper we will show how one can use Portable Stimulus and testing Standard (PSS) to write tests for HW verification environments (not only SW driven SoCs). The example will contain testbenches implemented in Specman and SystemVerilog, and tests generated by Perspec, Cadence PSS tool. We will show both the practical techniques, as well as methodology discussion.
 Speaker: Efrat Shneydor - Cadence Design Systems, Inc.
 Authors: Efrat Shneydor - Cadence Design Systems, Inc.
Slava Salnikov - Ben-Gurion Univ. & Bengal Engineering and Science Univ., Shibpur
Liran Kosovizer - Texas Instruments
Shlomo Greenberg - Ben Gurion University
5.3Designing a PSS Reuse Strategy
The recently-released Accellera Portable Test and Stimulus Standard (PSS) promises to boost verification reuse by allowing a single description of test intent to be reused across IP block, subsystem, and SoC verification environments, and provides powerful language features to address verification needs across the verification levels and address the specific requirement of verification reuse. However, language features on their own do not guarantee productive reuse of test intent. This paper describes methodology and a planning process to minimize duplicated effort and maximize the reuse benefits of adopting the Accellera Portable Test and Stimulus Standard.
 Speaker: Matthew Ballance - Mentor, A Siemens Business
 Author: Matthew Ballance - Mentor, A Siemens Business