29 - 30 October, 2019

Holiday Inn Munich City Centre

Munich, Germany

Event Details

MP Associates, Inc.
TUESDAY October 29, 11:45 - 13:15 | Forum 6
EVENT TYPE: TUTORIAL
SESSION 7T
Tutorial 7: UVM-SystemC – Functional Coverage & Constrained Randomization

Speakers:
Stephan Gerth - Bosch Sensortec GmbH
Muhammad Hassan - DFKI
Thilo Vörtler - COSEDA Technologies
Manuel Soto - Fraunhofer IIS, Institutsteil EAS
Organizer:
Stephan Gerth - Bosch Sensortec GmbH

UVM-SystemC is an implementation of the Accellera UVM standard originally implemented in SystemC. Standardization efforts of UVM for SystemC (named UVM-SystemC) have gained momentum to the point that multiple public review releases were released in the past years.

UVM-SystemC can be used with CRAVE, a C++ and SystemC constraint randomization library. However, standardized functional coverage aspects are currently missing within UVM-SystemC. In the meantime, AMIQ publicly released FC4SC, a functional coverage library aimed at SystemC under Apache License, which closes this important gap.

This tutorial will introduce the basic concepts and will give in-depth examples on how to apply CRAVE & FC4SC with UVM-SystemC, to address the current challenges in ESL design and verification environments.

Currently, the Accellera VWG is working on the standardization of a common randomization layer and a definition of functional coverage for UVM SystemC.

Summary, intended audience

This tutorial will be presented in three sections. In the first introductory section, several key mechanisms of constraint randomization and functional coverage in UVM contexts are shown to bring the audience to a common basic knowledge level. The basic concepts of the Universal Verification Methodology (UVM) will be presented and how constrained randomization and functional coverage can improve verification efforts. The knowledge on how to effectively combine and apply UVM, constrained randomization and functional coverage are the key to enable the verification of complex systems. Additionally, the re-use aspect of optimal verification results will be shown, especially when the design-under-test changes but contains similar interfaces.

The past and current standardization efforts within the Accellera Verification Working Group will be presented to show the evolution of UVM-SystemC within the working group. Further motivation and examples are given, showing how SystemC users can benefit from a standardized UVM implementation within their SystemC environment in their daily verification needs, especially considering an updated constrained randomization implementation and a publicly available functional coverage implementation. The current state of the proof-of-concept implementation will be shown and how it can be applied in current design flow setups.

The second part of the tutorial will present in-depth examples: First a combined application of constrained randomization and functional coverage using the above-mentioned libraries with UVM-SystemC, and second, a verification IP library approach by extensively relying on the re-use aspect of UVM-SystemC in addition to functional coverage for verification sign-off.

The final section will discuss the ongoing development of the proof-of-concept implementation and the language reference manual to show clearly where UVM-SystemC is headed and what has been already achieved in the past activities. As a closing item, future standardization topics, such as constrained randomization and functional coverage, within the Accellera Verification Working Group and further application fields of UVM-SystemC will be discussed to give the audience an outlook. The intended audience includes managers, system and verification engineers and architects with a basic knowledge in SystemC and/or UVM, which are interested to further improve their system-level verification practices.