WEDNESDAY October 30, 13:15 - 14:45 | Forum 7
EVENT TYPE: REGULAR SESSION
Harry Foster - Mentor, A Siemens Business
|8.1||Overcoming Challenges in SoC RTL Verification of USB Subsystem|
|In this paper we present an overview of the flow that SoC verification of USB Subsystem should follow in order to make the best compromise between SoC verification quality and verification time. We strongly suggest reuse of IP verification environment at SoC level, randomization of stimuli where it is possible as well as creating directed power scenarios, performance tests, and use cases. We also emphasize the importance of setting IP verification environment inside SoC verification testbench and reusing IP test scenarios. There are several issues which can occur during USB verification process due to backdoor enumeration, scaledown timings usage, error response check, low-power states testing, performance measurement. We discussed the root causes and suggested a way to mitigate the numbered issues. Also, we present a list of verification points that needs to be covered inside SoC verification of USB Subsystem to lower the risk of having uncovered bugs.|
|Speaker:||Tijana R. Misic - Elsys Eastern Europe d.o.o.
|Authors:||Tijana R. Misic - Elsys Eastern Europe d.o.o.
Marko J. Misic - Univ. of Belgrade
|8.2||Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined Nettype|
|This paper presents an implementation of Cadence’s EEnet structured SystemVerilog User-Defined Nettype (UDN) for electrical modeling that has been used to create real-number (RNM) models of drivers and loads part of the analog circuit involved in power regulation of power management systems. Structured UDN overcomes the natural limitations in modeling loading effects imposed by scalar Verilog-AMS wreal nettypes. This modeling technic enables verification teams to run Digital Mixed-Signal (DMS) simulations with loading effects in power regulation circuits, previously only possible in expensive Analog Mixed-Signal (AMS) simulations. The new capability along with the benefits of a significant improvement in simulation performance enables development teams to execute simulation-based concept studies, wide range of scenario variations and early sign off of the regulation circuits without the need of AMS simulations.|
|Speaker:||Alvaro Caicedo - Texas Instruments, Inc.
|Authors:||Alvaro Caicedo - Texas Instruments, Inc.
Sebastian Fritz - Texas Instruments, Inc.
|8.3||Covering the Last Mile in SoC-Level Deadlock Verification|
|Verifying the absence of System-on-Chip (SoC) deadlocks when integrating a wide variety of IP blocks and interconnect fabrics from various internal and third-party sources is a daunting challenge. Current solutions are typically composed of a combination of technologies such as full-chip simulation, emulation and hardware prototyping. However, deadlock scenarios often occur in rare cases that involve several preconditions occurring in sequence and with specific timing. Consequently, deadlock bugs may only be triggered in extreme corner-case conditions, which are resistant to discovery by traditional methods. In this paper we present a formal verification solution that exploits the exhaustive nature of formal analysis to overcome this resistance and deliver the confidence required for sign-off.|
|Speakers:||Dhruv Gupta - Oski Technology, Inc.
Konstantinos Liatakis - u-blox AG
|Authors:||Jef Verdonck - u-blox AG
Konstantinos Liatakis - u-blox AG
Khaled Nsaibia - u-blox AG
Dhruv Gupta - Oski Technology, Inc.
Sagar Dewangan - Oski Technology, Inc.
Tarun Upadhyay - Oski Technology, Inc.
HarGovind Singh - Oski Technology, Inc.
Roger Sabbagh - Oski Technology, Inc.