27 - 28 October, 2020

Virtual Conference

Event Details

MP Associates, Inc.

TUESDAY October 29, 11:45 - 13:15 | Forum 7

Tutorial 8: QED & Symbolic QED: Pre-Silicon Verification, Post-Silicon Validation, Industrial Results
Thomas Klotz - Bosch Sensortec GmbH

Subhasish Mitra - Stanford Univ.
Eshan Singh - Stanford Univ.
Keerthikumara Devarajegowda - Infineon Technologies AG
Subhasish Mitra - Stanford Univ.

This tutorial presents an end-to-end approach to pre-silicon verification and post-silicon validation of digital systems: the Quick Error Detection (QED) technique for post-silicon validation and debug, and the Symbolic QED technique for pre-silicon verification. Several industrial case studies (from AMD, Infineon, Intel and Freescale/NXP) will be covered. Practical experience in using these techniques for pre-silicon verification of safety-critical automotive designs at Infineon will be emphasized.

QED drastically reduces error detection latency, the time elapsed between the occurrence of an error caused by a bug and its manifestation as an observable failure. Symbolic QED combines QED principles with a formal engine for both pre- and post-silicon validation. These techniques are effective for logic design bugs and electrical bugs inside processor cores, hardware accelerators, and uncore components (cache controllers, memory controllers, interconnection networks or power management units).

Results from several commercial and open-source designs demonstrate:

  1. For billion transistor-scale designs, Symbolic QED detects and localizes difficult logic design bugs automatically in only a few (3-7) hours during pre-silicon verification.
  2. For open-source RISC-V processor cores, Symbolic QED detects (previously unknown) real logic design bugs within minutes automatically.
  3. An industrial case study on commercial automotive designs (at Infineon) shows that Symbolic QED detects all difficult logic design bugs while enabling 60-fold improvement in verification productivity (2 person-days using Symbolic QED vs. several person-months using conventional industrial flow).
  4. QED drastically improves error detection latencies of post-silicon validation tests by up to 9 orders of magnitude, from billions of clock cycles to very few clock cycles, and simultaneously improves bug coverage.
  5. QED-aided debug techniques automatically localize bugs in billion-transistor-scale designs during post-silicon debug, e.g., one can automatically narrow down the location of an electrical bug to a handful of flip-flops (~18 for a design with 1 million flip-flops), in only a few (~9) hours.