WEDNESDAY October 30, 3:15pm - 4:45pm | Forum 4
EVENT TYPE: REGULAR SESSION
|9.1||UVM based Hardware/Software Co-Verification of a HW Coprocessor via Host Execution Techniques|
|While UVM generalized adoption provides solutions for metric driven verification at IP and subsystem level, there is still a need to co-verify hardware subsystems together with the low level software drivers. If virtualization techniques, ISS as well as emulators address this need, they can be expensive, complex to setup. This paper presents a generic hardware/software co-verification approach using existing UVM verification IPs and allowing to run low level software without the needs for ISS based SystemC virtual platforms nor tools such as QEMU. We present how we run C code on the host machine and connect it to any UVM verification IP to develop reusable system level tests, while taking the benefits of SystemVerilog and UVM. This technique has been applied to a hardware accelerator which integrates a soft core processor, DMA IPs controlled by the vendor software drivers and a matrix MACs that serves as a coprocessor.|
|Speaker:||Francois Cerisier - Aedvices Consulting
|Author:||Francois Cerisier - Aedvices Consulting
|9.2||Customizing UVM agent to support multi-layered TDM & protocols|
|This paper addresses implementation issues faced when dealing with layered agent architecture and channelized agent definition. Advanced methodologies will be demonstrated using advanced UVM capabilities, which most basic agent’s implementation in the industry don't commonly used. We will also mention some problems that UVM does not give any solution and need to be addressed by using alternative techniques. Additionally, the paper we will analyze in-depth the relation between the main agents elements driver-sequencer-sequence (the so called UVM “magical” triangle) and how it operates, from the most basic agents' setup through the more advanced usage cases.|
|Speaker:||Amit Pessach - Veriest Solutions Ltd.
|Author:||Amit Pessach - Veriest Solutions Ltd.
|9.3||Methodology for checking UVM VIPs|
|The paper presents one possible way for more detailed checking of VIPs written in UVM/SV. If we develop a VIP for some interface for specific project, we are going to work on, then we probably won’t verify it thoroughly – we will just integrate it in verification environment (VE) and debug together with the rest of the VE and DUT. If the goal is to create reusable component that will be used in many other projects, or we do it for a customer and the component will be our product, then we need to check all its functions. This methodology enables self-checking test environment for all main VIPs' functions. By following the methodology, we can easily find many potential VIPs bugs and issues in development phase. This way we improve quality of our product and reduce debug time when our VIPs are used in different levels of verification.|
|Speaker:||Milan Vlahovic - Veriest Solutions Ltd.
|Author:||Milan Vlahovic - Veriest Solutions Ltd.