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DVCon Europe Announces Keynotes for 10th Anniversary Conference

Munich, Germany – 4th September 2023- The Design and Verification Conference & Exhibition Europe (DVCon Europe), sponsored by Accellera Systems Initiative, has announced its keynote speakers for the 10th anniversary event on November 14th and 15th in Munich.   The two selected industry luminaries are Philippe Notton, CEO and founder of SiPearl, and Michaela Blott, senior fellow at AMD Research. 

Philippe will discuss ‘Energy-efficient High-Performance Compute at the Heart of Europe’, covering the European Processor Initiative (EPI) and explaining how SiPearl, the private company born inside the EPI, is building the energy-efficient HPC dedicated microprocessor that will power Europe’s exascale supercomputers.

Michaela’s keynote is entitled ‘Pervasive and Sustainable AI with Adaptive Computing’ and will examine the challenges of sustainability, pervasiveness, agility and diversity.  Highly optimised AI systems are needed in order to address not only performance scalability and the needs of a broad range of diverse applications with the necessary agility, but also a reduction in carbon footprint.

“Both keynotes are a great match with the program and scope of DVCon Europe, and we are really happy to have two industry experts presenting their vision in these emerging areas,” said Martin Barnasconi, general chair of the DVCon Europe steering committee.

Philippe Notton is the CEO and founder of SiPearl, a French company building the world’s first energy-efficient HPC-dedicated microprocessor, designed to work with any third-party accelerator, whether that is a GPU, artificial intelligence or quantum chip.  He has worked for market-leading groups such as Thomson, LSI Logic and STMicroelectronics, as well as a successful start-up, MStar Semiconductor, sold to MediaTek in 2012 for four billion US dollars.

Michaela Blott is a Senior Fellow at AMD Research and leads a team of international scientists driving research in computer architectures for AI, green AI, and agile compiler stacks.  She has over 25 years’ worth of experience in leading-edge computer architecture and advance FPGA and board design, in research institutions (ETH Zurich and Bell Labs) and development organisations.

Registration for the event is now open at:  with reduced rates until 1st October.


The Design and Verification Conference & Exhibition in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, and one of several DVCon events around the globe, DVCon Europe brings chip architects, design & verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design. For more details, visit Follow #dvconeurope on Twitter.

DVCon around the world:

  • DVCon Taiwan – September 7, 2023
  • DVCon India – September 12-14, 2023
  • DVCon China – September 20, 2023
  • DVCon Europe – November 14-15, 2023
  • DVCon U.S. – March 4-7, 2024
  • DVCon Japan – June 20, 2024


Accellera Systems Initiative (Accellera) is an independent, not-for profit organization, dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit For membership information, please email Follow @accellera on Twitter or to comment, please use #accellera.

ACCELLERA GLOBAL SPONSORS: Cadence; Mentor, A Siemens Business; Synopsys

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Accellera Systems Initiative and DVCon are trademarks of Accellera Systems Initiative Inc. All other trademarks and trade names are the property of their respective owners.