Oren Katzir, VP, Application Engineering & Business Development

Oren leads Real Intent’s Application Engineering (AE) team that supports the sales team and customers. He brings to his new position more than 15 years of experience in engineering management, SoC and ASIC design, and development of SoC design tool flows. Previously, Oren was an engineering manager at Intel, leading an SoC engineering team. He also held engineering management positions at Sagantec, Silicon Design Systems, Transchip and Silicon Value. Oren holds a BS in computer engineering from the Technion-Israel Institute of Technology.

Vardan Vardanyan, Field Applications Engineer

Vardan started his career in the chip design industry as a mixed-signal designer at Epygi Labs. His experience includes stints as ASIC Digital Designer at Synopsys, InterMotion Technology, and CAE at Synopsys. Now Vardan helps customers effectively utilize Real Intent’s tools for their chip design projects and works with R&D in developing new features. Vardan graduated from Yerevan State University, Faculty of Radiophysics.

Introduction

Simulation-based testing has been the go-to approach for checking nearly everything through targeted tests in the ever-evolving verification methodologies. Its effectiveness has been undeniable and continues to play a critical role in verification landscape. However, it has its limitations. The number of possibilities it can cover remains limited compared to the complete set of potential behaviors, regardless of the number of tests or clever techniques used.

Today, static verification has become an indispensable companion to simulation, formal methods, and other verification techniques, excelling in various specific applications. Its scope has expanded beyond traditional timing analysis, linting, and clock domain crossing (CDC) checks. This expansion has been made possible by the continuous advancements in the power and versatility of static tools and the growing complexity of modern designs. Some verification challenges that were previously addressed by throwing more resources, such as people, licenses, and machines at the problem, have now surpassed the capabilities of conventional methods for confident signoff.

Summary of the content of the tutorial

This tutorial explores several emerging static signoff technologies and their applications in verification flows across both large and small design and verification organizations. These technologies are shaping how various companies approach verification coverage, offering valuable insights and efficiencies that complement existing methodologies.

By leveraging the strengths of static verification alongside other verification techniques, engineers and organizations can enhance their verification coverage, ensuring robust and reliable designs in the face of increasing design complexity. As the field continues to evolve, staying up-to-date with the latest static signoff advancements will be crucial in maintaining a competitive edge in the semiconductor industry.

The tutorial teaches new verification areas where static sign-off methodologies are evolving and getting deployed to increase efficiency and coverage of verification.

• Asynchronous Logic sign-off flows beyond CDC
• DFT Compliance, checking and enabling shift left using static sign-off
• Archiectural Compliance using static sign-off
• Connectivity checking using static-signoff

• Glitch checking metdhology using static-signoff
• Efficient functional sign off by automatic assertion generation for RTL building blocks using static methods
• Advanced methodology to identify X-initialization source errors and fix them to prevent the error from propagating

The tutorial then dives deep into specific industry use cases and examples, demonstrating how the industry is adopting these new approaches in the real world.

• Nvidia’s Asynchronous Logic Sign-Off Flows Beyond Structural CDC
• Kinara and Alif Semi – Shift Left DFT sign-off methodology for Edge AI Processor
• Palo Alto Networks – advanced X-propagation methodology to identify X-initialization source errors and fix them to prevent the error from propagating.
• Renesas – Efficient functional sign off by automatic assertion generation for RTL building blocks
• Real Intent with multiple customers – Connectivity, Glitch and architectural compliance using static-signoff.

The tutorial is designed to benefit audience members and enable them to enhance the state of verification practice in their workplace.

Intended Audience:

RTL Designers and managers, Verification engineers and managers, SoC designers and verification engineers, Chip Architects, Clocks and Reset designers and architects