The growing inclusion of mixed-signal components in large SoC verification efforts necessitates using advanced verification concepts from the digital verification world, such as Universal Verification Methodology (UVM), in mixed-signal verification. This requires exploring the ability to build scalable analog/digital abstractions and related interfaces, resulting in much higher performance with mixed-signal verification.
We will introduce the UVM-AMS methodology and show how to adapt existing UVM environments to work with three abstractions of a mixed-signal design. We will also highlight some unique Cadence technologies that make it easier to adopt UVM-AMS.
The Accellera UVM-AMS Standard will define an architecture and methodology to extend UVM testbenches from digital-only applications to DMS/real-number and AMS designs. This technical workshop will walk the audience through a working example that shows how to migrate an existing UVM testbench for a digital design to a UVM-MS testbench for a DMS and an AMS design. It will also preview how Cadence verification tools will implement this standard to expand the ecosystem for AMS verification and allow users to create and share compatible verification components and use them in existing UVM environments.
Join us in exploring new frontiers and building scalable methodologies for high-performance mixed-signal verification.
Solutions Group Director – AE
Product Validation Architect