29 - 30 October, 2019

Holiday Inn Munich City Centre

Munich, Germany


DVCon Europe 2019

Welcome Message

Joachim Geishauser
DVCon Europe 2019 General Chair
Welcome Message From The General Chair


I am pleased to welcome you to the 2019 edition of the Design and Verification Conference & Exhibition in Europe!

Also this year DVCon Europe will highlight applications and trends in system-level design and verification of electronic systems and integrated circuits. DVCon Europe is a technical and industry-centric conference where users, experts, and professionals meet to share best practices on methodologies, technologies and EDA standards such as UVM, SystemC, Portable Stimulus, IP-XACT, and more.

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Best Paper Awards

First Place:

5.2 Portable Stimuli Over UVM, Using Portable Stimuli in HW Verification Flow

Speaker: Efrat Shneydor - Cadence Design Systems, Inc.
Efrat Shneydor - Cadence Design Systems, Inc.
Slava Salnikov - Ben-Gurion University & Bengal Engineering & Science University
Liran Kosovizer - Texas Instruments
Shlomo Greenberg - Ben Gurion University

Second Place:

8.2 Enabling Digital Mixed-Signal Verification of Loading Effects in Power Regulation using SystemVerilog User-Defined Nettype

Speaker: Alvaro Caicedo - Texas Instruments, Inc.
Alvaro Caicedo - Texas Instruments, Inc.
Sebastian Fritz - Texas Instruments, Inc.

Third Place:

9.2 UVM Based Hardware-Software Co-Verification of a HW Coprocessor using Host Execution Techniques

Speaker: Francois Cerisier - Aedvices Consulting

Francois Cerisier - Aedvices Consulting
Arnaud Brasset - Thales Research and Technology





Conference Information

Tutorial & Proceedings Distrirbution

DVCon Europe Conference Papers and Tutorial presenter slides will be delivered electronically. The proceedings will be available online until Friday, 20 December 2019.

To access: http://proceedings.dvcon-europe.org

Username and password will be provided to registered conference attendees.

Conference Impressions and Photo's

2019 Photos


2019 SystemC Evolution Day View agenda and for additional information