Edwin Dankert, ARM Ltd.
Erwin de Kock, NXP Semiconductors
Devender Khari, Agnisys
Jean-Michel Fernandez, Arteris IP
Michael Velten, Infineon
Thomas Steininger, Intel
This tutorial explains basic usage of IP-XACT IEEE 1685-2022 for IP re-use and integration flows. It includes best practices from EDA vendors, IP providers, and IP integrators.
This tutorial addresses the IP-XACT user community by explaining the data model underlying the standard. This SoC data model unifies logical and physical connectivity as well as memory map and registers which enables the standard to be used as a single source of truth to automate large parts of SoC front-end design and verification flows.
The tutorial contains two slots. The first slot addresses IP-XACT concepts that are relevant to understand the overall SoC data model such as
- Design and Design Configurations
- Bus and Abstraction Definition
- Describing Connectivity
- Component Memory Maps and Registers
- Component Address Spaces and Bus Interface Bridges
- Type Definitions
The second slot addresses industrial practices from EDA vendors, IP providers, and IP integrators, specifically, Agnisys, Arteris, Infineon, and Intel.
The following topics will be covered:
- Agnisys – Spec to SoC : IP generation and integration using IP-XACT 2022
- Arteris – NoC modeling using IP-XACT 2022
- Infineon – IP-XACT based 3rd Party IP Integration Flow
- Intel – Intel’s Use Of IP-XACT For Integration Of 3rd Party IP