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How to leverage the power of MATLAB from Functional Verification Test Benches

Speaker Bio: Tom Richter joined MathWorks in Germany 2011 and worked 10 years as a Training Engineer for Model Based Design, Signal Processing, Communications, and Code Generation. With a strong focus on ASIC and FPGA design, he also developed training courses for HDL code generation and HW/SW co-design.
Since 2021, Tom works as an Application Engineering Specialist for HDL and System-on-Chip.

Tom has a Master of Engineering degree from the University of Ulster in Belfast and a Diploma of Electrical Engineering from the University of Applied Sciences in Augsburg.

As the complexity of digital designs continues to increase, verification engineers often need to use a combination of techniques to ensure that the design is thoroughly tested and meets the required specifications. The use of automated tools and methodologies is becoming increasingly popular to address these challenges.

There are several techniques used in verification, including formal verification, emulation, and simulation on which we will focus in this tutorial. Test bench environments are typically written in HDL languages such as SystemVerilog, Verilog, or VHDL and include non-synthesizable components, such as stimuli generators, drivers, scoreboards, and monitors. In many cases it is convenient to describe these components using non-HDL languages and environments such as MATLAB, C, or Python since those come with extensive domain-specific off-the-shelf libraries. For example, a stimulus generator component can be modelled in C. Similarly, a scoreboard component can be written in MATLAB to compare the actual output of the design against the expected output and additionally make use of MATLAB’s rich visualization options such as spectrum analyzer, constellation diagrams, and other scopes. These non-HDL components can be integrated into the test bench and used in conjunction with simulation to verify the design.

Moreover, in many domains such as signal processing, image processing and communications, MATLAB is the de facto standard language to explore, evaluate, and design the architecture and the algorithms of the corresponding systems and ICs. In these cases, it is beneficial to reuse the available MATLAB functions within the verification test benches, rather than re-implementing the same functionalities from scratch in SystemVerilog, C or other HDLs. Other than saving time, this also ensures consistency between the MATLAB and the verification environments. In this tutorial we will show how to call MATLAB functions from an HDL simulator and how to generate SystemVerilog DPI-C-based components or even whole UVM test benches from MATLAB code.