2018 Call For Papers - Closed
The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier conference for system architects, concept engineers, software developers, design and verification engineers, and IP integrators to share the latest methodologies and technologies in the practical use of EDA and IP languages and standards used in electronic design.
The focus of this highly technical conference is on the industrial application of specialized design and verification languages such as SystemC, SystemVerilog, VHDL, UVM or e; assertions in SVA or PSL; the use of AMS languages; design automation using IP-XACT; and the use of general purpose languages C and C++.
This call for papers solicits presentations that are highly technical and reflect real life experiences in using EDA languages, standards, methodologies and tools. Industry applications of interest include (but are not limited to) automotive, mobile communication, aerospace, healthcare, chip-cards, consumer and power electronics. Submissions are encouraged in (but not restricted to) the four topic areas listed below.
Topic Area 1: System-level design
- Virtual and hardware-assisted prototyping
- Hardware/software/embedded co-design
- System-on-chip and network-on-chip design
- High-level synthesis from ESL languages
Topic Area 2: Verification & Validation
- Verification process, reuse and resource management
- Methods bridging between verification and validation
- Hardware/software co-verification
- Advanced methodologies, testbenches, and flows (e.g., UVM, HDLs, HVLs)
- Formal and semi-formal V&V techniques
Topic Area 3: IP Reuse and Design Automation
- Interoperability of models and/or tools
- IP tagging, protection or security
- SoC and IP integration methods, flows, and tools
- Configuration management of IPs (including different abstraction level)
- Flow and tool automation (e.g., IP-XACT)
Topic Area 4: Functional Safety & Security
- Methods and flows for functional safety standard compliance (e.g., ISO 26262, DO-254)
- Safety and security in verification and validation
- Requirements-driven design and verification including traceability
- New methods and tools supporting functional safety and security
Topic Area 5: Mixed-signal & Low-power Design & Verification
- AMS modeling for concept and system-level design
- Application of mixed-signal extensions in verification (e.g., UVM-MS)
- Real-number modeling approaches
- Self-checking testbenches in analog verification
Paper Submission Process
Note: New Submission Guidlines for DVCon Europe 2018
An initial submission is required before the full paper.
In general, please provide enough details so that the Technical Program Committee can evaluate the potential quality and interest of your proposed presentation at DVCon Europe.
The initial submission should include:
- Title: The paper title.
- Contact information: Name, affiliation, phone number and email address for all authors and speakers.
- Short Abstract: Outline that clearly states the context and motivation of your contribution, max. 150 words.
- PDF Upload: 2 pages minimum without diagrams/pictures/etc required. If you would like to include diagrams/pictures/etc. the maximum amount of pages you can submit is 8. In your PDF, please include:
- Related Work: Identify other work on which this submission will be built, and the novelty of the paper.
- Application: Clearly describe the technical contribution, reflect real life experiences, and its industrial application.
- (Preliminary) results: Summarize the results. State how these differ from previous work or state-of-the-art on the same subject.
- Conclusions: Summarize major conclusions and findings presented in the paper.
- Industry or Academic: Selection if the submission is Industry or Academic
- Approval Agreement Confirmation: Confirmation that if accepted you are able to present the material you have submitted.
Accepted authors will be invited and agree to do the following:
- Submit the final version of the paper (max. 8 pages) after incorporating feedback from the TPC (July 31, 2018)
- Register for the conference
- Submit a copyright form
- All accepted authors agree to present an oral or poster presentation at the conference (October 24-25, 2018).
Please note: Consistent with the requirements for other DVCon Europe presentations, your presentation may contain your company logo only on the title slide, and should use the provided templates.
Please do your initial submission via the Navigation Center by EXTENDED DEADLINE of April 22, 2018. - Submission site is now closed.
- April 22, 2018: Deadline for initial submission - Submission site is now closed.
- May 30, 2018: Accept/Reject Notification sent to all authors.
- June 20, 2018: Full paper due for review by TPC
- September 5, 2018: Final Paper Due
- October 24-25, 2018: Conference
- October 24, 2018: Tutorials & Exhibition.
- October 25, 2018: Technical papers sessions, poster session, exhibition.
DVCon Europe honors the Best Paper/Presentation and Best Poster submissions. The awards will be selected by the attendees at DVCon Europe based on the quality of both the paper and the presentation.
More information on DVCon Europe can be found on www.dvcon-europe.org
- Alexander Rath, Infineon
- Matthias Bauer, Infinieon
- Mark Burton, GreenSocs