DVCon Europe 2015 Proceedings

DVCon Europe 2015 Proceedings

Below are presentations, papers, and posters from DVCon Europe 2015. You may download individual items below or download all items at once.

Jump to: Keynote | Tutorials | Presentations & Papers | Poster & Papers

Keynote

Road To Self Driving Cars Hans Adlkofer - Infineon Technologies AG Slides

Tutorials

T1: Advanced UVM Tutorial - Taking Reuse to the Next Level

Mark Litterick Jason Sprott - Verilab, United Kingdom Jonathan Bromley - Verilab, United Kingdom Tutorial

T2: System - Level Modeling for Today and Tomorrow with SystemC

Accellera Systems Initiative SystemC Standards Update Martin Barnasconi - NXP Philipp A. Hartmann - Intel Stephan Schulz - Fraunhofer Tutorial
Virtual Platform(s) Simulation: an Open-Source, Reusable, Affordable and Structured Approach based on TLM/CCI Guillaume Delbergue - GreenSocs/IMS Bordeaux Mark Burton - GreenSocs (Not available Online)
What is needed on top of TLM-2 for bigger Systems? Jerome Cornet - STMicrolectronics Martin Schnieringer - Robert Bosch GmbH Tutorial

T3: Applying Design Patterns to accelerate development of reusable, configurable and portable UVCs

Paul Kaunds - EnSilica Ltd., United Kingdom Tutorial

T4: Methodology of Communication Protocols Development: from Requirements to Implementation

Irina Lavrovskaya - St. Petersburg State University of Aerospace Instrumentation, Russia Valentin Olenev - St. Petersburg State University of Aerospace Instrumentation, Russia Tutorial

T5: UVM goes Universal - Introducing UVM in SystemC

Stephan Schulz - Fraunhofer IIS/EAS, Germany Thilo Vörtler - Fraunhofer IIS/EAS, Germany Martin Barnasconi - NXP Tutorial

T6: Accellera Standards Technical Update

Uwe Simm - Cadence Design Systems Sharon Rosenberg - Cadence Design Systems Erwin de Kock - NXP Philipp A. Hartmann - Intel Tutorial

T7: Verifying Functional, Safety and Security Requirements (for Standards Compliance)

Mike Bartley - Test and Verification Solutions, United Kingdom Tutorial

T8: Easier UVM: Learning and Using UVM with a Code Generator

John Aynsley - Doulos, United Kingdom Tutorial

T9: FPGA Debug Using Configuration Readback

Mike Dini - Dini Group, USA Tutorial

T10: Advanced, High-Throughput Debug From Design to Silicon

Gordon Allan - Mentor Graphics, USA Michael Horn - Mentor Graphics, USA Tutorial

T11: Golden UPF - Preserving Power Intent From RTL to Implementation

Himanshu Bhatt - Synopsys, USA Harsh Chilwal - Synopsys, USA Tutorial

Panel/T12: The Functional Verification Roadmap: Where Will We Be in Five Years?

Mike Bartley - TVS Lauro Rizzatti Raik Brinkmann - OneSpin Solutions Colin McKellar Imagination Technologies Holger Busch - Infineon Technologies Paul Dempsey (Moderator) - Tech Design Forum

T13: The How To’s of Advanced Mixed-Signal Verification

John Brennan - Cadence Design Systems, USA Thomas Ziller Kawe Fotouhi - Cadence Design Systems, Germany Ahmed Osman - Cadence Design Systems, Germany Tutorial

T14: UVM hardware assisted acceleration with FPGA co-emulation

Alex Grove - Aldec, United Kingdom Tutorial

T15: SystemVerilog Assertions Verification

Ionuț Ciocîrlan - AMIQ Consulting, Romania Andra Radu - AMIQ Consulting, Romania Tutorial

Presentation & Papers

Session TA1: Advanced Verification & Validation

TA1.1: Is Your Testing N-wise or Unwise? Pairwise and N-wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus Jonathan Bromley - Verilab Kevin Johnston - Verilab Paper Presentation
TA1.2: UVM Light: A Subset of UVM for Rapid Adoption Stuart Sutherland - Sutherland HDL Gordon Allan - Mentor Graphics Tom Fitzpatrick - Mentor Graphics Paper Presentation
TA1.3: An Efficient Verification Framework for Audio/Video Interface Protocols Noha Shaarawy, Mustafa Khairallah, Khaled Khalifa, Hany Salah, Amr Salah - Boost Valley Maged Ghoneima - Ain Shams University Paper Presentation
TA1.4: A Novel Processor Verification Methodology Based on UVM Abhineet Bhojak, Tejbal Prasad, Stephan Herrmann - Freescale Semiconductor Paper Presentation
TA1.5: Integration of Modern Verification Methodologies in a TCL Test Framework Matteo De Luigi, Alessandro Ogheri - Ogheri Consulting Paper Presentation
TA1.6: Virtual Models for Software and Firmware Development and Validation of a Complex IP within System Context Rocco Jonack - Intel Paper Presentation
TA1.7: OSVVM and Error Reporting Jim Lewis - SynthWorks Presentation
TA1.8: Leveraging the UVM Register Abstraction Layer for Memory Sub-System Verification Tudor Timisescu - Infineon Technologies Uwe Simm - Cadence Design Systems Paper Presentation
TA1.9: Closing the Loop from Requirements Management to Verification Execution for Automotive Applications Walter Tibboel, Jan Vink - NXP Semiconductors Paper Presentation

Session TA2: System Level Design & Verification

TA2.1: Boosting SystemC-based Testbenches with Modern C++ and Coverage-Driven Generation Hoang M. Le, Rolf Drechsler - University of Bremen Paper Presentation
TA2.2: Virtual Prototyping in SpaceFibre System-on-Chip Design Elena Suvorova, Nadezhda Matveeva, Ilya Korobkov, Alexey Shamshin, Yuriy Sheynin - Saint-Petersburg State University of Aerospace Instrumentation Paper Presentation
TA2.3:The Application of Formal Technology on Fixed-Point Arithmetic SystemC Designs Sven Beyer, Dominik Strasser, David Kelf - OneSpin Solutions Paper Presentation
TA2.4: Automated SystemC Model Instantiation with Modern C++ Features and sc_vector Ralph Görgen - OFFIS Philipp A. Hartmann - Intel Wolfgang Nebel - Carl von Ossietzky University of Oldenburg Paper Presentation

Session TA3: IP Reuse & Design Automation

TA3.1: Universal Scripting Interface for SystemC Rolf Meyer, Jan Wagner, Rainer Buchty - TU Braunschweig Mladen Berekovic - C3E, TU Braunschweig Paper Presentation
TA3.2: An Easy VE/DUV Integration Approach Uwe Simm - Cadence Design Systems Paper Presentation
TA3.3: Web Template Mechanisms in SOC Verification Rinaldo Franco, Alberto Allara - STMicrolectronics Paper Presentation

Session TA4: Analgo/Mixed-Signal Design & Verification

TA4.1: Comprehensive AMS Verification Using Octave, Real Number Modelling and UVM John McGrath, Patrick Lynch, Ali Boumaalif - Xilinx Paper Presentation
TA4.2: Integrating a Virtual Platform Framework for Smart Devices Valerio Guarnieri, Francesco Stefanni, Franco Fummi - EDALab Michelangelo Grosso, Davide Lena - ST-POLITO Angelo Ciccazzo, Giuliana Gangemi, Salvatore Rinaudo - STMicrolectronics Paper Presentation
TA4.3: Wave Digital Filter Modeling for Complex Automotive Sensor Load Case Verification Andrei Basa, Thang Nguyen, Dirk Hammerschmidt - Infineon Technologies Paper Presentation

Session TA%: RTL Simulation Techniques

TA5.1: Accelerating RTL Simulation Techniques Lior Grinzaig - ADVA Optical Networking Paper Presentation
TA5.2: Challenges of VHDL X-propagation Simulations Karthik Baddam - Imagination Technologies Piyush Sukhija - Synopsys Paper Presentation

Session TP1: Design for Functional Safety

TP1.1: A Meta-Model-Based Approach for Semantic Fault Modeling on Multiple Abstraction Levels Michael Schwarz - TU Kaiserslautern Moomen Chaari, Bogdan-Andrei Tabacaru, Wolfgang Ecker - Infineon Technologies Paper Presentation
TP1.2: Who Takes the Driver Seat for ISO 26262 and DO 254 Verification? Avidan Efody - Mentor Graphics Paper Presentation
TP1.3: An Automated Formal Verification Flow for Safety Registers Holger Busch - Infineon Technologies Paper Presentation
TP1.4: Achieve Complete SoC Memory Map Verification Through Efficient Combination of Formal and Simulation Techniques Clemens Roettgermann, Peter Limmer, Michael Rohleder - Freescale Semiconductor Paper Presentation

Session TP2: Low-Power Techniques

TP2.1: Power Aware CDC Verification of Dynamic Frequency and Voltage Scaling (DVFS) Artifacts Mark Handover, Jonathan Lovett, Kurt Takara - Mentor Graphics Paper Presentation
TP2.2: Refining Successive Refinement: Improving a Methodology for Incremental Specification of Power Intent Desinghu Ps, Adnan Khan - ARM Gabriel Chidolue, Erich Marschner, Gustav Bjorkman - Mentor Graphics Paper Presentation

Posters & Papers

P1.1: New Trends in RTL Verification: Bug Localization, Scan-Chain-Based Methodology, GA-Based Test Generation

Khaled Mohamed - Mentor Graphics Paper Poster

P1.2: Simplifying UVM in SystemC

Thilo Voertler - Fraunhofer IIS/EAS Thomas Klotz - Bosch Sensortec Felix Assmann - Bosch Sensortec Karsten Einwich - COSEDA Technologies Paper Poster

P1.3: Designing the Future With Efficiency

Axel Scherer - Cadence Design Systems Junette Tan - PMC Sierra Paper

P1.4: UVM and Emulation: How To Get Your Ultimate Testbench Acceleration Speed-up

Ahmed Yehia - Mentor Graphics Hans van der Schoot - Mentor Graphics Paper Poster

P1.5: A Concept for Expanding a UVM Testbench to the Analog-centric Toplevel

Felix Assmann - Bosch Sensortec Axel Strobel - Bosch Sensortec Hans Zander - Cadence Design Systems Paper Poster

P1.6: Efficient Constrained Random Generation of Address Blocks

Meenakshy Ramachandran - Synopsys Paper Poster

P1.7: Paving a Path to Hardware-Based Acceleration in a Single UVM Environment

Axel Scherer - Cadence Design Systems Mark Azadpour - Western Digital Paper

P1.8: A SystemC-based UVM Verification Infrastructure

Mike Bartley - Test and Verification Solutions Harshavardhan Narla - Test and Verification Solutions Paper Poster