Testbench Automation : How to Create a Complex Testbench in a Couple of Hours

Testbench Automation : How to Create a Complex Testbench in a Couple of Hours
In 2014, the semiconductor industry passed an important milestone. For the first time, the average engineering team had more verification engineers than designers. This means that any improvement in the efficiency of verifications teams has a significant impact on overall project costs and time to market.
In the past two decades, the industry has converged on two complementary strategies to verify increasingly complex SoCs : the reuse of testbenches from subsystem level to SoC level, and the use of advanced verification techniques such constrained random, assertions, and verification management. The key technology that enables these two strategies is the UVM.
Despite its success and proliferation, experience shows us that there are two main problems with this approach. The first is that there is a significant learning curve associated with the adoption of UVM, and the second is that even for UVM experts, creating the necessary infrastructure, getting it up and running, and achieving coverage closure is a time consuming and error prone process.
This tutorial introduces three new technologies which significantly reduce the time to create a reusable testbench infrastructure. These three technologies are integrated into a single comprehensive flow that significantly improves the efficiency of the whole testbench creation process.
In this tutorial, you will learn how to create a complex testbench in a couple of hours. In particular, you will learn:
• How to use UVM-F code generation to rapidly build reusable testbench infrastructure for simulation and emulation
• How to use a VIP Configurator to shorten the bring up time for industry standard protocols
• How Portable Stimulus shortens the time to create efficient, systematic scenario-level stimulus
You will also hear from industry experts who have successfully used this testbench automation flow on their projects.
This tutorial is intended for verification engineers, architects and managers who are interested in making significant improvements to the overall efficiency of their verification process.

Event ID: 
d3615763-f326-4220-814c-7907a27fcad6
Event Type: 
Tutorial
Location: 
Forum 6
Event Time: 
Monday, October 16, 2017 -
16:00 to 17:30
Session Number: 
15
Session Number: 
15
Session Number Suffix: 
T
confID: 
234
Event Sponsor Image URL: 
https://dvcon.org/sites/dvcon-europe.org/files/Mentor-ASB-Logo-Black-Hires.png