Virtual Prototypes and Platforms - A Primer

Today’s electronics devices are dominated by 'system on chips' (SoCs) where software outweighs more and more in terms of amount of lines-of-code (LOC) and of effort to create and validated it. To allow for short product cycles virtual prototypes and platforms (VPs) are developed to start software development before silicon is available or to validate design decisions during the initial stages of RTL design. This requires the modeling and simulation of the system’s components and environment at various levels of abstraction, representativeness, and accuracy. Certainly the availability of VPs will allow changing the development approach in other areas as well.

This tutorial aims to highlight challenges and opportunities in the development and deployment of VPs from a practical point of view. Use cases are not only in the semiconductor vendor domain but also at its customers.

The first part focuses on the clarification of the terms virtual prototype and virtual platform and sheds some light on the foundation of both. Essential for VP development are standards as well as tools and IPs adhering to them. This allows assembling and developing VPs at various levels of abstraction and accuracy. Various modeling styles like untimed (UT), loosely timed (LT) or approximately timed (AT) can be used and even mixed within a single VP to achieve the desired accuracy and simulation performance.

The second part presents use cases of virtual prototypes and platforms for both semiconductor vendor and their customer. Various engineering groups and roles in the VP development and adoption can be identified, such as IP authors, platform authors/IP integrators, and platform users/SoC integrators/system integrators. During the design phase these groups use VPs (amongst others) for architectural exploration, performance analysis and validation, functional verification and early software (esp. firmware) development. Depending on these use cases the requirements for VPs are different and there may be trade-offs i.e. between performance and accuracy.

But the availability and use of virtual platforms allows changing the system software development approach for both system integrators and users of the SoCs. Modern software development principles in embedded software development like test-driven-design (TDD) and continuous integration (CI) are enabled by virtual platforms. Using common strategies like Hardware-in-the- loop (HIL) typically don’t scale well enough and impose some fundamental restrictions for these approaches. For the software developer VPs typically provide better debugging capabilities as well as reproducibility and by this ease the development itself. When necessary other pre-silicon environments can be augmented by implementing parts of system as VP, while executing components for instance on FPGAs
Some aspects of the aforementioned possibilities will be illustrated with demonstrations to highlight key features.

The third part of the tutorial will wrap-up and summarize the advantages of using a virtual prototypes and platforms in the discussed use cases over other approaches such as FPGA prototyping, emulation or HIL. Limitations of VPs will be identified and discussed as well as how the various approaches to hardware/software validation and verification augment each other.

Event ID: 
afbcab87-667f-4c81-b4b1-9a9a777c455b
Event Type: 
Tutorial
Location: 
Forum 4
Event Time: 
Monday, October 16, 2017 -
11:30 to 13:00
Session Number: 
5
Session Number: 
5
Session Number Suffix: 
T
confID: 
234