We are in the era of automation explosion, and the semiconductor industry is at the forefront. While certain automation has given increased productivity and efficiency, could there be kinds of automation that has resulted in drop in productivity and team morale? Are there certain areas in the semiconductor industry, especially in the front end development where judicious care is required on what we automate and what we do not?
The demand for Solid State Drives (SSD) is growing both in the Enterprise and Client storage markets. SSD based on NAND Flash technology is a non-volatile storage that can be electrically erased and reprogrammed. NAND Flash technology provides higher durability than Hard Disk Drives (HDD), while providing access times similar to DRAM. However, it has also important limitations with regard to the amount of times that a memory block can be written before it starts wearing out.
In this technical tutorial we will see details of how Cadence and MathWorks toolsets can be used together to provide an integrated flow for mixed-signal systems, supporting both top-down design and bottom-up verification. This session includes live examples (ADCs, PLLs, and RF PAs), and will be presented by engineers from both companies. Attendees will gain a full appreciation of the technologies available and how they can be applied into their day-to-day work.
The tutorial will be a mixture of normal presentation and an ongoing demo/live example to support the presentation.
The topic is "code generation" which is a well-known discipline but done in a more sophisticated way to ease maintenance and re-usability. This is obtained by leveraging from EMF (Eclipse Modelling Framework) and utilizing this framework to build a proper model driven SW flow showing the benefits.
Today’s electronics devices are dominated by 'system on chips' (SoCs) where software outweighs more and more in terms of amount of lines-of-code (LOC) and of effort to create and validated it. To allow for short product cycles virtual prototypes and platforms (VPs) are developed to start software development before silicon is available or to validate design decisions during the initial stages of RTL design. This requires the modeling and simulation of the system’s components and environment at various levels of abstraction, representativeness, and accuracy.
Building on our well-received foundation-level tutorial Formal Verification – Too Good to Miss presented at DVCon Europe 2016, this year’s session will cover some of the more advanced techniques and workflow patterns that have proven valuable in our own formal verification work.
This tutorial will present the latest developments and features of the SystemC Analog/Mixed-Signal (AMS) extensions, which has been released as IEEE Standard 1666.1 in 2016. The SystemC AMS standard is defined in a language reference manual (LRM) defined as C++ class library, which can be used for electronic system-level (ESL) design and modeling for use by system architects and engineers, who need to address complex heterogeneous systems that are a hybrid between analog, digital and software components.
With the growing complexity of today’s SoCs, teams are facing intense time pressures for SoC verification closure, with engineers on the lookout for better verification and debug methodologies. As verification teams migrate to SystemVerilog and UVM class-based testbenches for higher efficiency and increased verification reuse across projects, debug methodology needs to scale accordingly to fully realize the benefits of this migration.
In this technical tutorial, we will focus on practical applications of Verdi debug innovations:
Much of the history of electronic design automation (EDA) has involved replacement of manual effort by automated processes. Place-and-route tools replaced hand layout, logic synthesis supplanted gate-level netlists, and constrained-random testbenches reduced or eliminated hand-written test vectors. Standardized formats used as input to the automation tools include SystemVerilog, Property Specification Language (PSL), and the Universal Verification Methodology (UVM).
Today’s SoC (ASIC or FPGA) designs are no longer purely hardware; they have recently taken a turn towards containing a significant amount of the software stack. Co-verification of hardware and software is put at greater importance when compared to other requirements in the verification plan. Before such a design is taped-out, it can be verified and validated at speeds near real operating conditions with peripherals and external devices connected using FPGA prototyping boards instead of simulation models. However, preparing a robust FPGA prototype is not a trivial task.