Tutorial 6 - UVM Mixed Signal Extensions – Sharing Best Practice and Standardization Ideas

During the last couple of years, various proposals have been presented at DVCon events showing AMS extensions for UVM as attempt to enrich and improve the verification of mixed-signal products and applications. Although all proposal have a similar goal, to make UVM more mixed-signal aware, they all differ in the concept definition and implementation choices made.
This tutorial brings all contributors of these UVM mixed-signal proposals together, to share their best practices and discuss if a path to standardization is feasible.

Tutorial 5 - Accellera Portable Test and Stimulus: The Next Level of Verification Productivity is Here

Up until now verification teams had been unable to reuse tests as their efforts progressed from virtual platforms to RTL, block-level to system-level or from simulation to emulation, prototyping or silicon. The advent of UVM, constrained-random verification and functional coverage improved the reusability of portions of the verification environment, but these advances have not been able to enable reuse of verification intent throughout the product development process.

Tutorial 4 - Machine Learning Introduction and Exemplary Application in Embedded Wireless Platforms

Machine Learning Introduction and Exemplary Application in Embedded Wireless Platforms

Tutorial 3 - Efficient use of Virtual Prototypes in Hardware/Software Development and Verification

Software development for embedded systems is becoming an increasingly challenging task, which calls for advanced design methods and tools to overcome productivity pains. Software developers have to cope with continuously growing complexity, instruction execution on multiple cores, a large number of hardware interactions (i.e. sensors & actors) and limited visibility into the device.

Tutorial 2 - UVM Audit: Assessing UVM Testbenches to Expose Coding Errors and Improve Quality

Does your UVM codebase contain hidden traps that may undermine current or future projects?

Working on client projects we have seen many verification environments that superficially claim to follow UVM best practice, but don’t stand up to expert scrutiny – for example:

Tutorial 1 - Case Study of Verification Planning to Coverage Closure @Block, Subsystem and System-on-Chip Level

Verification Planning and achieving coverage closure goals on time and under budget is one of the most challenging assignments in functional verification. Complicating this task is the increasing popularity of platform-based design, where IPs are extensively parameterized to enable end-user customization and differentiated derivatives.
Metrics is the key to success and we provide concrete examples that illustrate the value of Metrics at each stage.

Alexander Rath

Alexander Rath

Candi Wooldridge

Yang Xu

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