New demanding applications like ADAS, infotainment, and sensor fusion are driving growth in automotive semiconductors. These innovative features require both high compute power as well as predictability, which can only be delivered by heterogeneous architectures. We observe a trend towards multi-SoC Electronic Control Units (ECUs), where a high performance compute cluster, often running multiple embedded OSes, is integrated along with a traditional MCU cluster, running a real-time OS to deliver on predictability and timing constraints.
Application-specific adaptability of electronic systems demand for new design solutions. On the rise are automated firmware-based methodologies. From the application perspective this allows for flexible adaption to meet today’s multiple conflicting requirements, such as performance and power. This tutorial discusses techniques targeting the optimization of memory subsystems as well as the HW/SW interface under timing and power budgets. Then, it focuses on efficient VP-based simulation techniques complemented by formal verification approaches taking the firmware into account.
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 members building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
During the last couple of years, various proposals have been presented at DVCon events showing AMS extensions for UVM as attempt to enrich and improve the verification of mixed-signal products and applications. Although all proposal have a similar goal, to make UVM more mixed-signal aware, they all differ in the concept definition and implementation choices made.
This tutorial brings all contributors of these UVM mixed-signal proposals together, to share their best practices and discuss if a path to standardization is feasible.
Up until now verification teams had been unable to reuse tests as their efforts progressed from virtual platforms to RTL, block-level to system-level or from simulation to emulation, prototyping or silicon. The advent of UVM, constrained-random verification and functional coverage improved the reusability of portions of the verification environment, but these advances have not been able to enable reuse of verification intent throughout the product development process.
In the late 1960s, Samuel Arthur, research scientist at IBM, first employed the term machine learning to define the ability of computers to learn from data without having been explicitly programmed. Starting from this statement, we briefly introduce in this tutorial the historical background of machine learning (ML) and some significant milestones achieved until now.
Software development for embedded systems is becoming an increasingly challenging task, which calls for advanced design methods and tools to overcome productivity pains. Software developers have to cope with continuously growing complexity, instruction execution on multiple cores, a large number of hardware interactions (i.e. sensors & actors) and limited visibility into the device.
Does your UVM codebase contain hidden traps that may undermine current or future projects?
Working on client projects we have seen many verification environments that superficially claim to follow UVM best practice, but don’t stand up to expert scrutiny – for example:
Verification Planning and achieving coverage closure goals on time and under budget is one of the most challenging assignments in functional verification. Complicating this task is the increasing popularity of platform-based design, where IPs are extensively parameterized to enable end-user customization and differentiated derivatives.
Metrics is the key to success and we provide concrete examples that illustrate the value of Metrics at each stage.