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Open-Source Virtual Platforms for Industry and Research 

Nils Bosbach, RWTH Aachen University
Lukas Jünger, MachineWare GmbH
Rainer Leupers, RWTH Aachen University


The design of modern Systems-on-a-Chip (SoCs) is becoming increasingly complex, requiring simulation at an early stage to ensure correct functionality and performance. Virtual Platforms (VPs) are a valuable tool for simulating complete SoCs, enabling rapid prototyping, hardware/software co-design, and early software development and verification. To construct such simulations, the SystemC TLM-2.0 standard provides a set of interfaces that are widely used in the industry.

In this workshop, we present the Virtual Components Modeling Library (VCML)1, an open-source tool that builds on top of SystemC TLM-2.0 to provide a flexible framework for quickly developing and integrating new models for system-level simulations or entire systems from scratch. VCML includes a set of modeling primitives and component models that can be used to swiftly assemble system-level simulators for embedded systems, i.e., VPs, in a fast and efficient way. Its main design goal is to accelerate VP construction by providing commonly used features such as TLM sockets, interrupt ports, Input/Output (I/O) peripherals, and registers.

Based on these design primitives, TLM models for frequently deployed components are also provided, such as memories, memory-mapped buses, Universal Asynchronous Receiver/Transmitters (UARTs), etc. In addition, VCML offers so-called properties for runtime parametrization of models and systems, a logging and tracing API, debugger integrations and the VCML session protocol, which enables 3rd party tools, such as GUIs or CI libraries, to take control of the VP.

VCML is written in modern C++ and ships with an extensive unit testing suite. Nightly CI runs ensure backwards compatibility until SystemC 2.3.0a as well as compatibility with Intel and ARM host systems. VCML is licensed under the terms of the Apache-2.0 license to facilitate industrial use cases.

At the Institute for Communication Technologies and Embedded Systems (ICE) of RWTH University, we developed the ARMv8 VP An ARMv8 Virtual Platform (AVP64)2 . The VP is based on VCML and uses Quick Emulator (QEMU) as Instruction-Set Simulator. The architecture of the VP is shown in Figure 1.

The platform consists of a QEMU-based CPU and different peripherals, which are all part of VCML. The interconnection of the components is realized using TLM-2.0-based protocols for memory accesses and interrupts which are defined in VCML as well.


This workshop aims to demonstrate how a VP can be created using VCML, a library that provides a set of VP design building blocks. The workshop is structured into three main parts:

  • an introduction to the basic concepts and building blocks of VCML
  • integration with other tools
  • a demo of VPs built using VCML.

In the first part of the workshop, participants will learn about the module classes, parametrization principles, and different TLM-based interconnect protocols provided by VCML. They will also be introduced to different implementation decisions, such as the backends principle, which is supported by several modules. The goal of this part is to give participants a general overview of the design steps needed to create a VP using an exemplary system.

In the second part of the workshop, the focus will be on integrations with standard tools and workflows. Participants will learn about LUA scripting, debugger support for GDB and MCD-capable debuggers like Lauterbach’s TRACE32, and Python scripting. These integrations allow developers to extend the functionality of VCML and integrate it into their existing workflows seamlessly.

The final part of the workshop will allow participants to experience VPs built using VCML. They will be presented with the open-source ARM VP AVP64, and MachineWare’s RISC-V simulator SIM-V. Participants will have the opportunity to boot a RISC-V Android on SIM-V, demonstrating the versatility of VCML.

Overall, this workshop provides an in-depth look into creating VPs using VCML and how they can be integrated into existing workflows. It is an excellent opportunity for developers and engineers to learn about the capabilities of VCML and how it can be used to speed up the development and testing of complex embedded systems.