Panel: 5G Chip Design Challenges and their Impact on Verification

DVCon attendees are invited to learn about the unique challenges of designing chips that support 5G deployment for high-speed cellular networks as well as vertical industries like factories and agriculture. A panel of verification technology and 5G experts will share their knowledge of the current environment, citing practical lessons, real-world case studies and actionable insight into chip design for 5G applications.

The discussion will include examples of how varied end products impact design decisions and architectures. Panelists will suggest whether there is a one size fits all, customized designs or if customization relies on software to achieve application-specific requirements.

5G technology forces compliance with tighter functional objectives and even more demanding integration testing than prior communications technologies. Panelists will be asked to weigh in on the effectiveness of Open RAN and if it creates opportunities for more companies to unveil 5G products.

Such challenges could suggest an overhaul of today’s verification and validation environment. Panelists will be asked for their opinions on whether an overhaul of the design and verification environment is needed for 5G requirement or if the same flows that works for CPU, GPUs and other ASIC devices also works for 5G.

Audience participation will be encouraged.

Moderator

Gabriele Pulini
Product Marketing and Market Development
Siemens EDA

Panelists

Ashish Darbari
Founder and CEO
Axiomise

Oren Katzir
Vice President of Applications Engineering
Real Intent

Herbert Taucher
Head of Research Group
Siemens AG

Anil Deshpande
Associate Director
Samsung Semiconductor India 

Axel Jahnke
SoC R&D Manager
Nokia

Panel 1 - DVCon Europe 2022

Organizer

Carole Dunn / Nanette Collins