A symbiotic relationship exists between modern System-on-Chip (SoC) requirements and processor technology evolution. As SoCs are applied to a broader range of applications with specialized needs, for example safety and security in the case of automotive and medical electronics, processor suppliers must adapt their devices accordingly while ensuring that performance and power objectives continue to be met.
To meet these needs, processor clusters leverage specialized instructions and accelerators across coherent fabrics driven by performance optimized software. This has recently been augmented by the advent of open instruction set architectures and the inclusion of custom instructions. The impact of this evolution is most felt during the verification process. Ensuring instruction set compatibility and efficient load-store operation in processor that must meet ever more stringent SoC requirements has verification teams scrambling. Are we at a verification inflexion point where the whole process requires revamping?
Mike Bartley, a well-known verification technologist and commentator, will moderate this panel made up of verification experts on the frontline of SoC challenges. They will explore evolving SoC requirements, the impact of new processor developments and their own experience at meeting corresponding verification needs. Expert panelists from a leading processor provider and SoC integrator will compare their findings with two noted EDA SoC/processor verification company leaders. Attendees will learn what is coming in terms of SoC developments and strategies for dealing with these. Audience participation will be encouraged.
Mike BartleyTessolve (formerly CEO of TVS)
Moderator DVClub Europe and Verification Futures Bristol
Distinguished Engineer Verification, IBM
Application Engineering Specialist Imperas
Oxford United Kingdom
Director of Verification, Codasip Bath
CEO, Breker Verification Systems
San Jose, CA, USA
David Kelf / Nanette Collins