Panel Day 1: Assessing the Needs and Solutions for a Secure IC Supply Chain
There is ample evidence of counterfeit and fake electronic parts infiltrating the IC supply chain and being used in safety- and security-critical applications. The mil/aero industry has been concerned with the risk of hardware Trojans being inserted in third-party IP blocks and, therefore, IC designs for many years. In 2007, DARPA launched the TRUST in Integrated Circuits program, with the goal of developing technologies for use in military applications designed and fabricated under untrusted conditions.
The availability of trustworthy electronics is a prerequisite for innovation, from low-cost IoT devices to autonomous vehicles and critical infrastructure. Many countries have identified the IC supply chain as a national security concern beyond defense applications. As such, the semiconductor industry should develop processes and technology that provide objective and measurable evidence of trustworthiness. It is reasonable and desirable to expect that IP and SoC development organizations deploy state-of-the-art technology and processes dedicated to IC trust and assurance, and a critical component of this is the tools and methodologies employed in these processes.
Verification has evolved from functional test to include infrastructure, safety and now security assurance. Security assurance is particularly complex, given the broad range of vulnerability types, the numerous stakeholders within the supply chain, and the life cycle of hardware and software components.
Moderator Paul Dempsey and a panel of experts will discuss next-generation methods used to test IP blocks and encompassing systems to identify security weaknesses, vulnerabilities, and malicious logic. They will offer examples of verification flows that address trust and security challenges within the context of an implementable security strategy.
Paul Dempsey - Tech Design Forum
John Hallman - Member SAE G-32 Cyber Physical Systems Security Committee, OneSpin Solutions
Adnan Hamid - President and CEO/CTO, Breker Verification Systems
Rick O’Connor - President and CEO, OpenHW Group
Vivek Vedula - Principal HW Security Methodology Lead, Arm
Panel Day 2: Verification Challenges of an Exascale Supercomputer
Europe and the European Processor Initiative (EPI) consortium are taking a huge leap forward with the goal to design a low-power, high-performance exascale supercomputer. Many notable European companies are committed to a revolutionary new microprocessor architecture and roadmap for a well-implemented design.
The stakes are high. A secure and reliable microprocessor to support high-performance computing will need to meet the demands of a range of emerging complex applications. Those include artificial intelligence, connected mobility, storage, research, health, weather forecasting, energy, defense, chemicals, engineering, cybersecurity and smart cities as a start.
Achieving success will not be possible without robust verification. A new exascale supercomputer design creates far-reaching implications and potential consequences for today’s design verification flow that could require reimagining and overhauling each product segment. It may mean reeducation of verification engineers as well.
Chip design and verification experts from Europe and the U.S. will join moderator Jean-Marie Brunet from Mentor, a Siemens Business, for a discussion about the verification requirements of a new type of exascale supercomputer. At the end of the panel, they will attempt to define a specialized new verification flow to support the initiative.
Jean-Marie Brunet - Mentor, A Siemens Business
Christian Beckmann - ASIC Verification Manager, Global Big Data and Security Division, Atos
Mark Glasser - Member of the Technical Staff, Cerebras
Gajinder Panesar - Fellow, Mentor, A Siemens Business
Nasr Ullah - Senior Director of SiFive Performance Architecture for RISC-V Technology and Applications (SPARTA), SiFive
Ying-Chih Yang - CTO SiPearl
Roger Espasa - CEO SemiDynamics